Timeout management

The timing control needs some timeout for the error recovery. The timeout must check :

1. FT arriving if TRIG is set the first.
2. VAL arriving
3. REQ arriving

Four programmables timers are implemented : TIMER0 for the FT waiting, TIMER1 for the VAL waiting, TIMER2 and TIMER3 for the REQ waiting on each FERA branch. Each timer generate a timeout if the condition which is expected is not reached. These timeout are:

1. For TIMER0, TIMEOUT0:
   This timer is started by TRIG cleared by FT or the timeout.
   The range is 0-5 Sec and the step 500 nSec.
   This timer must be enabled or desabled by software to allow waiting for FT or not.
   On timeout, the FVI must :
   Clear the GATE and the FERA ADCs on each FERA branch if true.
   Clear the INHIBIT signal if true.
   Clear the REN signal if true.
   Assert RESET to the ancillary trigger.
   Clear the FTD signal if true.
2. For TIMER1, TIMEOUT1:
   This timer is started by TRIG cleared by VAL or the timeout.
   The range is 0-15 Sec and the step 500 nSec.
   This timer must be enabled or desabled by software to allow waiting of VAL or not.
   On timeout, the FVI must :
   Clear the GATE and the FERA ADCs on each FERA branch.
   Clear the INHIBIT signal if true.
   Clear the REN signal if true.
   Assert RESET to the ancillary trigger.
   Clear the VALD signal if true.
3. For TIMER2 and TIMER3, TIMEOUT2,TIMEOUT3:
   These timers are started by GATE on each FERA branch cleared by REQ or the timeout on each FERA branch.
   The range is 0-30 Sec and the step 500 nSec.
   On timeout, the FVI asserts REN to start the FERA readout.