VXI readout

The GIR manages the data transfer from the FVI FIFOs to the GIR FIFO. The FVI FIFOs size is 4Kbytes and 32 bit data format. The GIR manage also the VXI readout, that is the data transfer from the GIR FIFO through the VXI bus.
To take part in the current event data flow through the VXI bus, the FVI must:

1. Tell the GIR that the current event (started by TRIG) will be available by setting VALACK true on the falling edge of TRIG.
2. Latch the EVENT NUMBER from the four bits given by the GIR EVENT-IN output to the GIR EVENT-OUT input on the falling edge of VAL.

To transfer the data from the FVI FIFOs to the GIR FIFO the FVI must :

1. Tell the GIR that somes data will be available in the FVI FIFOs by setting START-READOUT true on the falling edge of TRIG. The GIR asserts REN-IN and waits for a data available in the first FIFO of the FVI.
   
2. When this data is available, the FVI sets DATA-READY. Then, the GIR writes this data in its FIFO and asserts DATA-ACK. At last, the FVI deasserts DATA-READY. This handshake is repeated until all the data from the first FVI FIFO are transfered to the GIR FIFO. Then the FVI desasserts START-READOUT and asserts END-READOUT which is connected to the START-READOUT of the second FVI FIFO.
3. On completion of the same handshake DATA-READY/DATA-ACK for the second FIFO, the FVI sets END-READOUT which is sent to the GIR.
4. If a REJECT or a timeout occure as explained in the next section, START-READOUT is cleared and END-READOUT is set by the FVI.
5. On completion of the readout, the GIR asserts LTRESET which clears VALACK.