Module Control Register

The 16 bits MCR must have the following bits to :

1. RESET the module, that is clear the FERA branches, clear the FIFOs, clear REN, assert LRESET and RESET.
2. VALIDATE or INHIBIT TIMER0 and TIMER1 to discard the fonctionnalities of the EUROBALL MASTER TRIGGER.
3. VALIDATE or INHIBIT the TEST MODE.
4. VALIDATE or INHIBIT the TEST functions to simulate REJECTand REQ on FERA branches 1 and 2.
5. Insert or separate the EINHIBIT for the INHIBIT action on the ancillary trigger.
   1. In the first case , there is a common dead time between every FERA crate, INHIBIT is sent to the ancillary trigger.
   2. In the second case, only a local INHIBIT inhibs the FVI. INHIBIT is not sent to the ancillary trigger.
   3. When INHIBIT is true TRIG, FT and VAL actions have not effect in the FVI, except for the counters (see counters).