Controls and timings

This section summarize the controls specification and specify the timing constraints. It identify the relationships among the events which control the FVI. The model used is the State Transition Diagram (STD). The figure 2.4 shows the description of the symbols used in a STD. The Timings give the mains phases in the FVI.

  
Figure 2.4: STD symbols

The figure 2.5 shows the timing for FT or VAL waiting, for REQ waiting and the timeout actions

  
Figure 2.5: TIMEOUTs for FT, VAL, REQ

The figure 2.6 shows the STD for RESET.

  
Figure 2.6: RESET

The figure 2.7shows the STD for CLR1 and CLR2.

  
Figure 2.7: CLR1 and CLR2

The figure 2.8 shows the STD for INHIBIT.

  
Figure 2.8: INHIBIT