This is the DPP register Config 0x8000

Configuration Register

  ITRG:
     Permits the propagation of the external trigger as gate from mother board to mezzanines  (bit 2)

  Test Mode:
     When enabled the input signal samples are replaced by a sawtooth test signal  (bit 3)

  Individual trigger:
     This bit must be set to 1   (bit 4)

  Pulse Polarity:
      Polarity of the input signal  (bit 9) 

  Dual Trace:
     When the oscilloscope mode is enabled it is possible to read two different waveforms from the FPGA. In this mode the samples of the two signals are interleaved - thus each waveform will be sampled at 50 Msps. When Dual Trace is disabled the signal selected by Virtual Probe 1 is sampled at 100 Msps. (bit 11)

  Oscilloscope:
     When enabled the digitizer acts as an oscilloscope. The readout data contains the sequence of the samples that belong to the signals selected by the Analogue/Virtual Probe options.  (bit 16)

  Baseline: 
     When enabled the baseline is saved into the event data.  (bit 17)

  Time Tag:
     When enabled the time tag (the zero crossing of the delta2 signal) of all the pulses is saved into the event data. (bit 18)

  Charge:
     When enabled the Qshort and Qlong are saved into the event data.  (bit 19)

  Digital Virtual Probe:
    There are several digital control signals in the algorithm implemented inside the FPGA. It is possible to save two of them in the event data.
    When enabled the analog probe samples are represented into 8 bits rather than 10 bits.  (bit 26)

  DVP #1:
    Digital Virtual Probe 1 - selects the probe to be shown.  (bits 22:20)

  DVP #2:
    Digital Virtual Probe 2 - selects the probe to be shown.  (bits 25:23)