DPP Algorithm Control (0x1n80)

Management of the DPP algorithm features. 


bit [16]:      Invert Input:   Individual settings for the input signal inversion. The DPP-PHA algorithm is designed to work with positive signals. The input signal polarity can be inverted inside the FPGA before applying the DPP algorithm.


bit [19:18]:   Trigger Mode:   Options available are:  
                     Normal - each channel can self-trigger independently from the other channels
                     Neighbour - each channel also triggers when either the previous or subsequent channel trigger
                     Coincidence - each channel saves the event only when a validation signal occurs in coincidence within its shaped trigger
                     Anti-coincidence - each channel saves the event only when a validation signal occurs in anti-coincidence within its shaped trigger

bit [22:20]:   Baseline Averaging window:   Number of samples for the baseline average calculation