Failure of VME interface on V1724 ================================= On starting acquisition [set Acquisition Control (0x8100) = 4] all VME accesses to the board return BERR status. Accesses to other boards in the crate are OK DTACK led on the V1724 is on permanently even when there is no activity on the VME backplane. Unable to recover since board VME interface is non responsive. Power cycle of VME crate needed to recover. The fault is intermittant. I am trying to obtain more information. Previously it was observed that if the Acquisition was stopped (0x8100 = 0) while a data readout was in progress (MBLT transfer) the VME interface would fail. This happened in nearly 100% of cases. The software was modified so that Acquisition stop would only occur when no MBLT transfer in progress. This change prevented failures. However if I manually set Acquisition Control (0x8100 = 0) under normal acquisition state then the VME interface fails as decribed. This does seem to be 100% reproducable. Slave module VME interface unstable when board using External clock taken from another V1724 ============================================================================================ I have master V1724 using internal clock and slave V1724 in which CLK Source DIP-SW is set to EXT. CLK OUT from master module is connected to CLK IN on slave module. CAENPLLConfig tool is used to program the AD9510 clock chip. Note that tool does not produce the window as shown on Page 21 of the V1724 manual (Rev 20; March 15 2010). Options used are INPUT PLL; Input Clock 50 MHz; VCXO frequency AUTO => 500 MHz; Output Sample 100 MHz; O/P clock enable; 50 MHz; no delay On Slave observe that CLKIN led is ON and PLL LOCK led is ON for both master and slave. On the Slave module I read Acquisition Status (0x8104). This returns 0x00a0 and/or 0x0120. If I repeatedly read this register bit 8 is not stable. If I attempt to acquire data reading the Event Output Buffer gives BERR after a small number of words (much less than the Event Size register returns). Reading Events Stored register (0x812c) => BERR. Also the PLL LOCK led is seen to go OFF and then ON. Acquisition Status 0xa0 => no PLL loss of lock; not ready 0x120 => PLL loss of lock; ready If I remove the CLK link cable between the modules then on the slave module PLL LOCK led is OFF. However Acquisition Status register now returns 0x0120 and is stable. PLL and ADCs are synchronised. I can collect data in this state and reading the Event Output Buffer is stable and gives good data. Data Buffering does not seem to be active ========================================= BUFF_ORG is set to 8 so expect 255 buffers of 2K samples each. Oscilloscope Mode is enabled. At no time is the contents of the Event Stored register (0x812c) other than 0 or 1. I setup the board and set Acquisition Control (0x8100) = 4. Input data causes a trigger. The module RUN, DRDY and BUSY leds come on. Event Stored is now 1. I read the data FIFO and obtain 1 event. Event Stored is now 0 and the Event Outout Buffer is now empty. Would appear that only 1 buffer is being used. Post Trigger register cannot be read ==================================== Using Post Trigger register (POST_TRG) at 0x1n14. [ n is the channel number; use 0x8014 for multicast write access] Write seems to be OK. The value written observed to effect data as expected. Read 0x1n14 always returns 0xffffffff. Bad Data ======== Observe sample data words such as 0x245fe460 (occurs 1 in 500 words with a trace of 2000 samples)) Would expect 0x245f2460 Bits 14 and 15 set = 1 when Bit 30 = 0 This is not expected from the event data format. Event with no trigger information (1 in 100 events) Channel Status register (0x1n88) incomplete =========================================== Memory full and memory empty (bits 0/1) seem OK. Other bits always 0 Chn and Chn+1 enabled (bits 3/4) return zero even when channels enabled. There are other issues when using the V1724 board with "real" data. However these are cases in which the current design and or specification of the firmware is limiting and will be reported as a separate document.