DPP Algorithm Control (0x1n80)

Management of the DPP algorithm features. 

bits [5:0]:    Trapezoid Rescaling: The trapezoid evaluated inside the FPGA can be represented as a 48 bit number, where the number of most significant bits depends on the trapezoid rise time (k) and on the input signal decay time (m). 15 bits over 48 are reported by the board as the energy value.
         The trapezoid rescaling N defined how many LSB are thrown away (ie right shift) before the trapezoid height is saved. This corresponds to a division by 2N. In normal conditions the value of N is such that 2N <= m*k < 2N+1.

bits [9:8]:    Decimation:    The input signal samples can be averaged within the number of samples defined by the decimation. This has the analogous effect as reducing the sampling frequency of the board. 

bits [11:10]:  Digital Gain:  The input samples are digitally multiplied by the Digital Gain value. 

bits [13:12]:  Peak Mean:     Corresponds to the number of samples for the averaging window of the trapezoid height calculation. For a correct energy calculation the Peak Mean should be contained in the flat region of the Trapezoid Flat Top.

bit [15]:      Noise Rejection:  When enabled triggers are inhibited until the "Input Rise Time" duration is reached. In the case of noisy signals this feature can avoid triggering on noise on the rise time of the RC-CR2 signal which do not correspond to real signals. This feature also allows the use of lower values of the trigger threshold. 

bit [16]:      Invert Input:   Individual settings for the input signal inversion. The DPP-PHA algorithm is designed to work with positive signals. The input signal polarity can be inverted inside the FPGA before applying the DPP algorithm.

bit [17]:      Trigger on RC-CR or RC-CR2 signal:  The trigger normally fires on the zero crossing of the RC-CR2 signal. For fast input signals it is possible to set the trigger on the zero crossing of the RC-CR signal. 

bit [19:18]:   Trigger Mode:   Options available are:  
                     Normal - each channel can self-trigger independently from the other channels
                     Neighbour - each channel also triggers when either the previous or subsequent channel trigger
                     Coincidence - each channel saves the event only when a validation signal occurs in coincidence within its shaped trigger
                     Anti-coincidence - each channel saves the event only when a validation signal occurs in anti-coincidence within its shaped trigger

bit [22:20]:   Baseline Averaging window:   Number of samples for the baseline average calculation

bit [24]:      Self Trigger:  The self-trigger is always propagated to the mother board for coincidence logic and for the TRG-OUT front panel output. 
                              However it can be enabled or disabled for use by the channel to acquire the event. 

bit [25]:      Pseudo Event #1:  When this option is enabled a psudo-event is generated in the event of a Time Reset signal (S-IN). The event data is tagged to indicate the occurance. 

bit [26]:      Pseudo Event #2:  When this option is enabled a pseudo-event is generated in the event of a Time Stamp roll over. The event data is tagged to indicate the occurance.

bit [27]:      Pile-Up option:    When a pile-up occurs the board normally returns energy=0 (option=disabled).  When this option is enabled the energy is evaluated for piled-up events. Events are flagged as pile-up though a bit in the output data. The energy value is NOT corrected.