This is a read only status register. 


Acquisition Status (0x8104, R, C)
This register monitors a set of conditions related to the acquisition status. 
Bit Description
[1:0] Reserved.
[2] Acquisition Status. It reflects the status of the acquisition and
   drivers the front panel 'RUN' LED.
  Options are:
 0 = acquisition is stopped ('RUN' is off);
1 = acquisition is running ('RUN' lits).
[3] Event Ready. Indicates if events are available for readout.
   Options are:
  0 = no event is available for readout;
 1 = at least one event is available for readout.
NOTE: the status of this bit must be considered when managing the
readout from the digitizer.
[4] Event Full. Indicates if at least one channel has reached the FULL
   condition.
  Options are:
 0 = no channel has reached the FULL condition;
1 = the maximum number of events to be read is reached.
[5] Clock Source. Indicates the clock source status.
   Options are:
  0 = internal (PLL uses the internal 50 MHz oscillator as reference);
 1 = external (PLL uses the external clock on CLK-IN connector as
reference).
[6] PLL Bypass Mode. This bit drives the front panel 'PLL BYPS' LED.
   Options are:
  0 = PLL bypass mode is not active ('PLL BYPS' is off);
 1 = PLL bypass mode is active and the VCXO frequency directly drives
the clock distribution tree ('PLL BYPS' lits).
WARNING: before to operate in PLL Bypass Mode, it is recommended to
contact CAEN for feasibility.
[7] PLL Unlock Detect. It is the flag for a PLL unlock condition.
   Options are:
  0 = PLL has had an unlock condition since the last register read
 access;
1 = PLL hasn't had any unlock condition since the last register read
access.
NOTE: flag can be restored to 1 via read access to the Readout
Status register, 0xEF04.
[8] Board Ready. This flag indicates if the board is ready for
   acquisition (PLL and ADCs are correctly synchronised).
  Options are:
 0 = board is not ready to start the acquisition;
1 = board is ready to start the acquisition.
NOTE: this bit should be checked after software reset to ensure
that the board will enter immediately run mode after RUN mode
setting; otherwise, a latency between RUN mode setting and
Acquisition start might occur.
[14:9] Reserved.
[15] S-IN (VME boards) or GPI (DT/NIM boards) Status. Reads the current
    logical level on S-IN (GPI) front panel connector.
[16] TRG-IN Status. Reads the current logical level on TRG-IN front panel
    connector.
[31:17] Reserved