Run Mode: Software Controlled; Start and Stop of acquisition takes place on setting/resetting the Acquisition control bit. S-IN Controlled; If the acquisition is armed then the run starts when the S-IN signal is asserted and stops when the S-IN signal is inactive. If the acquisition is disarmed then acquisition then the S-IN signal is ignored. First Trigger; If the acquisition is armed then the run starts on the first trigger pulse (rising edge on TRG-IN); this pulse is not used as a trigger, actual triggers start from the second pulse. The stop of run is software controlled. GPIO Controlled; As for S-IN control but using GPIO. Acquisition: When in Software Controlled mode this acts as a run start/stop. For all other run modes the actual start/stop is controlled by an external signal as described. NOTE: At present only Software Control is supported by the acquisition system. Acquisition Control (0x8100, R/W, C) This register permits configuring the acquisition settings. Bit Description [1:0] Start/Stop Mode Selection. Options are: 00 = SW CONTROLLED. Start/stop of the run takes place on software command by setting/resetting bit[2] of this register; 01 = S-IN/GPI CONTROLLED (S-IN for VME, GPI for Desktop/NIM). If the acquisition is armed (i.e. bit[2] = 1), then the acquisition starts when S-IN/GPI is asserted and stops when S-IN/GPI returns inactive. If bit[2] = 0, the acquisition is always off; 10 = FIRST TRIGGER CONTROLLED. If the acquisition is armed (i.e. bit[2] = 1), then the run starts on the first trigger pulse (rising edge on TRG-IN); this pulse is not used as input trigger, while actual triggers start from the second pulse. The stop of Run must be SW controlled (i.e. bit[2] = 0); 11 = LVDS CONTROLLED (VME only). It is like option 01 but using LVDS (RUN) instead of S-IN. The LVDS can be set using Front Panel I/O Control register, 0x811C, and Front Panel LVDS I/O New Features register, 0x81A0. [2] Acquisition Start/Arm. When bits[1:0] = 00, this bit acts as a Run Start/Stop. When bits[1:0] = 01, 10, 11, this bit arms the acquisition; the actual Start/Stop is controlled by an external signal. Options are: 0 = Acquisition STOP (if bits[1:0]=00); Acquisition DISARMED (others); 1 = Acquisition RUN (if bits[1:0]=00); Acquisition ARMED (others). [3] Trigger Counting Mode Selection. Options are: 0 = only accepted triggers are counted; 1 = all triggers are counted. [4] Reserved. [5] Memory Full Mode Selection. Options are: 0 = NORMAL. The board is full whenever all buffers are full; 1 = ONE BUFFER FREE. The board is full whenever Nb-1 buffers are full, where Nb is the overall number of buffers in which the channel memory is divided. [6] PLL Reference Clock Source (Desktop/NIM only). Options are: 0 = internal oscillator (50 MHz); 1 = external clock from front panel CLK-IN connector. NOTE: this bit is reserved in case of VME boards. [7] Reserved. [8] LVDS I/O Busy Enable (VME only). The LVDS I/Os can be programmed to accept a Busy signal as input, or to propagate it as output. Options are: 0 = disabled; 1 = enabled. NOTE: this bit is supported only by VME boards and meaningful only if the LVDS new features are enabled (Bit[8]=1 in the Front Panel I/O Control register, 0x811C). LVDS I/O New Features register, 0x81A0, should also be configured for nBusy/nVeto. [9] LVDS I/O Veto Enable (VME only). The LVDS I/Os can be programmed to accept a Veto signal as input, or to transfer it as output. Options are: 0 = disabled; 1 = enabled. NOTE: this bit is supported only by VME boards and meaningful only if the LVDS new features are enabled (Bit[8]=1 in the Front Panel I/O Control register, 0x811C). LVDS I/O New Features register, 0x81A0, should also be configured for nBusy/nVeto. [10] Reserved. [11] LVDS I/O RunIn Enable Mode (VME only). The LVDS I/Os can be programmed to accept a RunIn signal as input, or to transfer it as output. Options are: 0 = starts on RunIn level; 1 = starts on RunIn rising edge. NOTE: this bit is supported only by VME boards and meaningful only if the LVDS new features are enabled (Bit[8]=1 in the Front Panel I/O Control register, 0x811C). LVDS I/O New Features register, 0x81A0, should also be configured for nBusy/nVeto. [31:12] Reserved.