| Register |
[namespace eval V1720 {
set html ""
# append html " | "
for {set i 0} {$i <= 7} {incr i} {
append html "n=$i | "
}
set html
}]
| Channel n Threshold (0x1n80) |
[namespace eval V1720 {
set html ""
# append html " | "
for {set i 0} {$i <= 7} {incr i} {
append html "[ReadRegister Ch$i.Threshold] | "
}
set html
}]
| Channel n Status (0x1n88) |
[namespace eval V1720 {
set html ""
# append html " | "
for {set i 0} {$i <= 7} {incr i} {
append html "[ReadRegister Ch$i.Status] | "
}
set html
}]
| Channel n AMC FPGA Firmware (0x1n8c) |
[namespace eval V1720 {
set html ""
# append html " | "
for {set i 0} {$i <= 7} {incr i} {
append html "[ReadRegister Ch$i.FPGARev] | "
}
set html
}]
| Channel n Buffer Occupancy (0x1n94) |
[namespace eval V1720 {
set html ""
# append html " | "
for {set i 0} {$i <= 7} {incr i} {
append html "[ReadRegister Ch$i.Bufs] | "
}
set html
}]
| Channel n DAC (0x1n98) |
[namespace eval V1720 {
set html ""
# append html " | "
for {set i 0} {$i <= 7} {incr i} {
append html "[ReadRegister Ch$i.DAC] | "
}
set html
}]
| Channel n ADC Configuration (0x1n9c) |
[namespace eval V1720 {
set html ""
# append html " | "
for {set i 0} {$i <= 7} {incr i} {
append html "[ReadRegister Ch$i.ADCConfig] | "
}
set html
}]
| Channel n Over/Under Threshold (0x1n84) |
[namespace eval V1720 {
set html ""
# append html " | "
for {set i 0} {$i <= 7} {incr i} {
append html "[ReadRegister Ch$i.OUThresh] | "
}
set html
}]
| Channel n ZS_THRES (0x1n24) |
[namespace eval V1720 {
set html ""
# append html " | "
for {set i 0} {$i <= 7} {incr i} {
append html "[ReadRegister Ch$i.ZSThresh] | "
}
set html
}]
| Channel n ZS_NSAMP (0x1n28) |
[namespace eval V1720 {
set html ""
# append html " | "
for {set i 0} {$i <= 7} {incr i} {
append html "[ReadRegister Ch$i.ZSNSAmp] | "
}
set html
}]
| Channel Configuration |
[namespace eval V1720 {
set html ""
append html "[ReadRegister Config] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Buffer Organization |
[namespace eval V1720 {
set html ""
append html "[ReadRegister BufferOrg] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Acquisition Window Size (CUST_SIZE) |
[namespace eval V1720 {
set html ""
append html "[ReadRegister CustomSize] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Acquisition Control |
[namespace eval V1720 {
set html ""
append html "[ReadRegister AcqControl] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Acquisition Status |
[namespace eval V1720 {
set html ""
append html "[ReadRegister AcqStatus] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Trigger Source Enable Mask |
[namespace eval V1720 {
set html ""
append html "[ReadRegister TrigSrcEnable] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Front Panel Trigger Out Enable Mask |
[namespace eval V1720 {
set html ""
append html "[ReadRegister FPTrigOutEnable] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Post Trigger |
[namespace eval V1720 {
set html ""
append html "[ReadRegister PostTrig] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Front Panel I/O Data |
[namespace eval V1720 {
set html ""
append html "[ReadRegister FPIOData] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Front Panel I/O Control |
[namespace eval V1720 {
set html ""
append html "[ReadRegister FPIOControl] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Channel Enable Mask |
[namespace eval V1720 {
set html ""
append html "[ReadRegister Enable] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| ROC FPGA Firmware Revision |
[namespace eval V1720 {
set html ""
append html "[ReadRegister FPGARev] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Events Stored |
[namespace eval V1720 {
set html ""
append html "[ReadRegister EventsStored] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Set Monitor DAC |
[namespace eval V1720 {
set html ""
append html "[ReadRegister MonitorDAC] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Board Info |
[namespace eval V1720 {
set html ""
append html "[ReadRegister BoardInfo] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Monitor Mode |
[namespace eval V1720 {
set html ""
append html "[ReadRegister MonitorMode] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Event Size |
[namespace eval V1720 {
set html ""
append html "[ReadRegister EventSize] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| VME Control |
[namespace eval V1720 {
set html ""
append html "[ReadRegister VMEControl] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| VME Status |
[namespace eval V1720 {
set html ""
append html "[ReadRegister VMEStatus] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Board ID |
[namespace eval V1720 {
set html ""
append html "[ReadRegister BoardID] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Max Events per BLT |
[namespace eval V1720 {
set html ""
append html "[ReadRegister BLTEventNum] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]
| Scratch Register |
[namespace eval V1720 {
set html ""
append html "[ReadRegister Scratch] | "
for {set i 1} {$i <= 7} {incr i} {
append html " | "
}
set html
}]