Here's the basic recipe for setting up and using the MyRIAD module. I will provide this as steps, rather than specific code, so as to avoid po lluting the discussion with the details of how any given system performs VM E transactions. To work with the MyRIAD, you need only be able to perform single-word A24/D16 VME transactions (reads and writes). As noted in sect ion 1.3 of the manual (copy attached for your convenience) the MyRIAD takes up a block of 16K addresses in the 24-bit address space, with the upper ei ght bits of the VME address set by a DIP switch. The MyRIAD modules we use here at DGS historically have been set to respond to addresses 0x550000 - 0x55FFFC. FIBER OPTIC LINK TO/FROM DIGITAL GAMMASPHERE 1) A bi-directional fiber runs from the Digital Gammasphere master trigger module to the MyRIAD, using a small front-panel paddle card that adapts from fiber to the RJ-45connector of the board. Communication occurs in both directions. The MyRIAD receives a continuous series of command frames from the master trigger, but in the vast majority of applications only uses the frames that broadcast the DGS timestamp. 2) The physical chipset used for the fiber communication extracts the clock of DGS's master trigger and makes it available to the MyRIAD FPGA. A clock multiplexer external to the FPGA allows the user to switch the logic of the MyRIAD between use of the local oscillator and use of the clock fro m the DGS master trigger, so that the timestamp of the MyRIAD then becomes perfectly locked to that of DGS. This is first explained in section 2.2 of the manual. 3) What your software will have to do for system initialization is the following: a. Ensure that the serial interface chip is in the correct state to r eceive information from DGS over the fiber. Normally at power up it is, so you need do nothing, but if your VME crate crashed or you just had a soft reset you might have to set some things. i. Read the SERDES COMMAND FORMAT register and verify that the register is set for DGS mode (see 7.1.14). ii. Read the SERDES CONFIG register (section 7.1.26) is set to the default value of 0x8063 as described. b. Read some status bits to verify that the MyRIAD is receiving inform ation from DGS over the fiber. i. Read the HARDWARE STATUS register (section 7.1.3) and examine the various bits. The SD LOCK bit tells you the state of the physical connection. This bit basically tells you whether the fiber is plugged in or not. c. Tell the MyRIAD to use the data and clock from the fiber. i. Veri fy that the PROPAGATION CONTROL register (see 7.1.22) is set to process SYN C commands. ii. Clear bit 15 of the SERDES CONFIG register (see section 7.1.26) to switch the cl ock, without changing the state of the other bits. I usually also set bit 7 (stringent lock). Do this by writing the value 0x0063 or 0x00E3. d. Clear state machine status bits, and then verify that the bits do n ot again set, to ensure that the state machine of the MyRIAD is correctly r eceiving the data from DGS. i. Writ e the value 0x002C to the PULSED CONTROL register (see 7.1.4) to simultaneo usly reset the FIFO, clear the trigger counter and reset the "lost lock" bi t in the HARDWARE STATUS register. ii. Read the HARDWARE STATUS register (section 7.1.3) to verify that the SD_SM LOCK and SD_SM_LST_LK bits are telling you that the MyRIAD is now properly locke d to the DGS master trigger and that the 50MHz data checking occurring in t he state machine finds no data errors. iii. Readi ng the SYSTEM TIMESTAMP registers (section 7.1.16) provides confirmation th at the MyRIAD timestamp is counting, but since the least significant bit co unts at 100MHz, obviously VME timing precludes using this for anything othe r than a base diagnostic. e. Set up the MyRIAD for the triggering activity desired. i. Set up the GATING register (section 7.1.10) for the correct trigger input the T S latch source for your application. f. Poll for events and read out timestamps. i. You may read the FIFO STATUS register (section 7.1.2) to directly look at FIFO flags, but be forewarned that in A24/D16 applications only one of the two F IFOs is used. ii. I usu ally recommend reading the FIFO COUNTER register (section 7.1.23) in case m ultiple events have been stored in the FIFO since the last poll. iii. You m ay also monitor the TRIG COUNTER register (section 7.1.24). iv. Other s ignals (e.g. FAG or even the NIM outputs of the MyRIAD) may be connected to the other NIM inputs and counted using the registers described in section 7.1.25. v. The FI FO is read out at address 0x1000 (see section 7.1.27) or you may use the la tched timestamp registers (section 7.1.13). The FIFO empty/full flags and the fact that you must read the FIFO a couple more times than you think you should have confused many. The data sheet referenced is some help.