| Register |
[namespace eval V1724PHA {
set html ""
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "n=$i | "
}
set html
}]
[namespace eval V1724PHA {
set html ""
append html ""
append html "| Channel n Algorithm Control (0x1n80) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.AlgorithmControl] | "
}
append html "
"
append html ""
append html "| Channel n Rise Time (0x1n58) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.InputRiseTime] | "
}
append html "
"
append html ""
append html "| Channel n Averaging Window (0x1n54) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.AvWindow] | "
}
append html "
"
append html ""
append html "| Channel n Decay Time (0x1n68) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.DecayTime] | "
}
append html "
"
set html
}]
[namespace eval V1724PHA {
set html ""
append html ""
append html "| Channel n Trapezoid Rise Time (0x1n5c) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.TrapRiseTime] | "
}
append html "
"
append html ""
append html "| Channel n Trapeziod Flat Top (0x1n60) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.TrapFlatTop] | "
}
append html "
"
set html
}]
[namespace eval V1724PHA {
set html ""
append html ""
append html "| Channel n Threshold (0x1n6c) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.Threshold] | "
}
append html "
"
append html ""
append html "| Channel n Peaking Time (0x1n64) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.PeakingTime] | "
}
append html "
"
set html
}]
[namespace eval V1724PHA {
set html ""
append html ""
append html "| Channel n RTD Window Width (0x1n70) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.RTDWinWidth] | "
}
append html "
"
append html ""
append html "| Channel n Trigger Hold Off (0x1n74) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.TrigHoldOff] | "
}
append html "
"
append html ""
append html "| Channel n Peak Hold Off (0x1n78) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.PeakHoldOff] | "
}
append html "
"
append html ""
append html "| Channel n Trigger Request Width (0x1n84) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.TrigWidth] | "
}
append html "
"
set html
}]
[namespace eval V1724PHA {
set html ""
append html ""
append html "| Channel n Pre Trigger (0x1n38) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.PreTrig] | "
}
append html "
"
set html
}]
[namespace eval V1724PHA {
set html ""
append html ""
append html "| Channel n Num Events per buffer (0x1n34) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.EvtsPerBuf] | "
}
append html "
"
set html
}]
[namespace eval V1724PHA {
set html ""
append html ""
append html "| Channel n Event Length (0x1n20) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.RecLen] | "
}
append html "
"
set html
}]
[namespace eval V1724PHA {
set html ""
append html ""
append html "| Channel n Trig Val Mask (0x81nm) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.TrigValMask] | "
}
append html "
"
set html
}]
[namespace eval V1724PHA {
set html ""
append html ""
append html "| Channel n AMC FPGA Firmware Revision (0x1n8c) | "
# append html " | "
for {set i 0} {$i < $NumChans} {incr i} {
append html "[ReadRegister Ch$i.FPGARev] | "
}
append html "
"
set html
}]
| FirmWare License |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister FirmWareLicense] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Board Configuration |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister Config] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Buffer Organization |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister BufferOrg] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Acquisition Control |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister AcqControl] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Acquisition Status |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister AcqStatus] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Board Fail Status |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister BoardFailStatus] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Trigger Source Enable Mask |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister TrigSrcEnable] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Front Panel Trigger Out Enable Mask |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister FPTrigOutEnable] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Acquisition Window Size (CUST_SIZE) (0x8020) |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister CustomSize] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Front Panel I/O Data |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister FPIOData] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Front Panel I/O Control |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister FPIOControl] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Channel Enable Mask |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister Enable] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| ROC FPGA Firmware Revision |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister FPGARev] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Set Monitor DAC |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister MonitorDAC] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Board Info |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister BoardInfo] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Monitor Mode |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister MonitorMode] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Event Size |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister EventSize] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Run Delay |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister RunDelay] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Veto |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister Veto] | "
# append html "berr | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| VME Control |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister VMEControl] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| VME Status |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister VMEStatus] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Max Events per BLT |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister BLTEventNum] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
| Scratch Register (0xef20) |
[namespace eval V1724PHA {
set html ""
append html "[ReadRegister Scratch] | "
for {set i 1} {$i < $NumChans} {incr i} {
append html " | "
}
set html
}]
[namespace eval V1724PHA {
set html ""
for {set i 0} {$i <= 0x4c} {incr i 4} {
append html "| Configuration ROM 0x[format %02x $i] | "
append html "[ReadRegister ConfigROM[format %02x $i]] | "
for {set j 1} {$j <= $NumChans} {incr j} {
append html " | "
}
append html "
"
}
for {set i 0x80} {$i <= 0x84} {incr i 4} {
append html "| Configuration ROM 0x[format %02x $i] | "
append html "[ReadRegister ConfigROM[format %02x $i]] | "
for {set j 1} {$j <= $NumChans} {incr j} {
append html " | "
}
append html "
"
}
set html
set html ""
}]