----------------------------------------------------------------------------- --- CAEN SpA - Front End R&D Division --- ----------------------------------------------------------------------------- This file is x720 FPGA Standard firmware revision history. x720 digitizer board houses two kinds of FPGA devices that are configured with a single programming file: - ROC FPGA is the mainboard FPGA for communication and trigger handling. - AMC FPGA is the mezzanine FPGA for ADC and channel memory management: there are eight of them, but they are loaded with the same firmware image. Release numbers are in the form X.X_Y.Y, where X.X is the motherboard FPGA release, while Y.Y is the channel mezzanine FPGA release. =============================================================================== INTERMEDIATE REVISIONS NOT PRESENT HERE ARE TO BE INTENDED FOR INTERNAL USE AND THEIR NOTES ARE APPENDED TO THE LATEST OFFICIAL REVISION =============================================================================== Release 4.16_0.15 =============================================================================== New Features / Changes : * ROC: (VME ONLY) Added feature to use VetoIn LVDS to disable TRGOUT generation, selectable by register Bug fix : * AMC: Solved a noise problem on channels in revision 0.14 =============================================================================== Release 4.14_0.14 =============================================================================== New Features / Changes : * AMC: Improved timing on TRGIN signal * AMC: Modified internal clock generation: CLKRAM generated pll, CLK125 generated with flip flop from DCLK0s,a copy of DCLK0 (adc clock). * ROC: Added option to have "UNLOCK" onto TRGOUT (used to trigger in PLL_LOCK_LOSS): reg 0x811c : bit[20]='1', bit[19:18]="01" (main probe) bit [17:16]= "11" (BUSY_UNLOCK). * ROC: Modified Board Fake bit: removed readout_timeout in generated "Board Fake" and modified localbus_timeout. * ROC: Added option to have "Extended Trigger Time Tag" or "Event Trigger Source" on "Pattern Field in the word2 of the Event Header (via bit[22:21] reg 0x811C). * ROC: (VME ONLY) FW for PCB rev >=4: added or modified Sync signal for new DC/DC Converters. * ROC: (VME ONLY) Added Force Reboot also for VME models * ROC: Added Buffer Occupancy Gain Register (0x81B4): monitor has 1024 step, 1 buffer = 2 exp(gain) steps. Default 0 (1 buffer -> 1 step). * ROC: Added LVDS_TRGOUT selection: LVDS_TRGOUT must be a copy of ACQ_TRG(GTRG) or a copy of TRG_OUT(lemo). * ROC: Modified TEST_IO register reading. * ROC: Optimized timing contraint on internal local bus communication bus for improved margins. * ROC: Optimized timing for nlCLR: signal registered and placed on pad. * ROC: Added feature to send Start_RUN (not delayed, for daisy chain) or Internal_RUN (delayed, for syncronization debug) * ROC: (VME ONLY): Optimized timing on LVDS I/O (signals registered and placed on pad) Bug fix : * ROC: Fixed error in reporting FULL Status (BUSY LED and FULL flag) when the board is not in run * ROC: Fixed a bug on USB communication (Only DT models affected). * ROC: (VME ONLY) Fixed a bug in LVDS I/O trigger selection for TRG-OUT propagation =============================================================================== Release 4.5_0.13 =============================================================================== New Features / Changes : * ROC: Added an automatic control of the fan speed (Desktop only) * ROC: Added automatic reload of PLL after a change of the clock source (ext/int) (Desktop only) * ROC: Added Board Fail bit in event header, and Error Monitor register 0x8178 Bug fix : * ROC: Corrected an error after the Clear command * ROC: Fixed issue in case of single channel register access during BLT * ROC: Modified TRGOUT (Front Panel) logic generation. =============================================================================== Release 4.1_0.12 =============================================================================== New Features / Changes : * ROC: Added a new management of front panel LVDS I/Os * ROC: Added Busy/Veto IN/Out; by default, the old LVDS I/O setting is kept for compatibility with previous versions * ROC: Added support for new models (x743, DT5720D/DT5720E/N6720D/N6720E/V1720F/ V1720G) * AMC: Deleted clearmem and clearblk and cleared files * ROC: Modified some timig constraint Bug fix : * ROC: Firmware not working for 2 channel versions of the desktop/NIM digitizers * ROC: Occasional communication error when restarting after an anomalous program interruption (e.g. process killed); added an internal timeout to recover * ROC: External trigger Mask not working * ROC: Occasional data readout error * ROC: Busy output on the LVDS I/Os not working with DPP firmware * ROC: PLL lock flag (0x8104[7]) not reporting current status of lock * ROC: Interrupts through optical link not working properly * ROC: DES mode not supported for model V1751C * AMC: Modified data and localbus clear to solve a bug in a stop/start run sequence =============================================================================== Release 3.4_0.11 =============================================================================== New Features / Changes : * Added dedicated register for signal vetoing: external trigger input can be completely disabled for any use. * S-IN signal usage heravily modified. Bug fix : * Fixed issues for start/stop acquisition. * Fixed issues for optikal link interrups propagation o na daisy-cahined link. * Minor bug fixing. =============================================================================== Release 3.2_0.10 =============================================================================== New Features / Changes : * New syncronous start for multiboard configuration with TRG-OUT/TRG-IN configuration fully implemented. Added possibility to start acquisition with a software trigger to the first board in the chain. Bug fix : * Fixed issue on optical link state machine. * Fixed timing issue that could cause proper synchronization between channels. =============================================================================== Release 3.1_0.9 =============================================================================== Bug fix : * (Only for V1720/VX1720) Fixed a major bug in VME interface that could generate misalignement on event readout. * Fixed issue on acquisition start/stop: data readout could not restart after a stop/start acquisition sequence. =============================================================================== Release 3.0_0.9 =============================================================================== New Features / Changes : * Optical link interface protocol upgraded to CONET2: CONET2 is NOT back compatible with previous CONET1 protocol. Check migration instructions on CAEN website or contact support.frontend@caen.it. * Changed run mode configuration bit usage(bit[1:0] of 0x8100 register): Mode "00" unchanged. Other modes changed to support improved multiboard run synchronization. * Downsampling feature discontinued. Bug fix : * Minor bug fixing ===============================================================================