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\begin{document}
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\samepage \begin{figure}[h]
\centerline{\psfig{figure=bloc_trig.eps}}

\label{bloc_trig}
\end{figure}
}

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\samepage \begin{figure}[h]
\centerline{\psfig{figure=ft_ancil.eps}}

\label{ft_ancil}
\end{figure}
}

{\newpage
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\samepage \begin{math}13 \mu \end{math}
}

{\newpage
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\samepage \begin{math}25 \mu \end{math}
}

{\newpage
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\samepage \begin{math}10 \mu\end{math}
}

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\samepage \begin{figure}[h]
\centerline{\psfig{figure=context.eps}}

\label{context}
\end{figure}
}

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\samepage \begin{tabular}{|c|c|c|c|}\hline
Name & Function & Logic & Timing\\  \hline\hline
RAW PARTICULE & Fast decision from Anc. Trigger & ? & ? \\  \hline
RAW GE & Raw Ge from Master Trigger & ? & ? \\  \hline
RESET & Clear Anc. Trigger & NIM & ? \\  \hline
INHIBIT & Discard FT and Val & NIM & set by TRIG\\ 
 & & & Cleared by last PASS \\  \hline
TRIG & Trigger from Ancillary & NIM & ? \\  \hline
REJECT & Anc. pileup rejection & NIM & Duration of FERA coding \\  \hline
ON/OFF & Anc. trigger input & NIM & - \\  \hline
WST & Fera write strobe & ECL & min 40 nS \\  \hline
WAK & Fera write ackn. & ECL & min 30 nS \\  \hline
CLR & Fera Clear & ECL & min width 5 nS \\  \hline
REQ & Fera Request & ECL & - \\  \hline
REN & Fera Ren & ECL & maintained during entire readout \\  \hline
PASS & Fera branch last Pass & ECL & - \\  \hline
GATE & Fera gate & ECL & set by TRIG \\ 
 & & & delayed from 0 to \begin{math} 20 \mu \end{math}Sec\\ 
 & & & Step 10 nSec \\ 
 & & & width from 10 nSec to 20 \begin{math}\mu \end{math}Sec \\ 
 & & & Step 10 nSec \\  \hline
FTD & Fast Trigger delayed & NIM & idem GATE \\  \hline
VALD & Validation delayed & NIM & idem GATE\\  \hline
FDATA & Fera Data from ADCs & ECL & - \\  \hline
FT & Fast Trigger EUROBALL & TTL & ? \\  \hline
VAL & EUROBALL Validation & TTL & ? \\  \hline
DAV & DATA available & TTL & - \\  \hline
G*/S & Go*/Stop signal & TTL & - \\  \hline
VDATA & Available data for VXI interf. & TTL & - \\  \hline
\end{tabular}
}

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\samepage \begin{math}\mu \end{math}
}

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\samepage \begin{figure}[h]
\centerline{\psfig{figure=dfd_fera_vxi.eps}}

\label{dfd_fera_vxi}
\end{figure}
}

{\newpage
\clearpage
\samepage \begin{tabular}{|c|c|c|c|}\hline
Name & Function \\  \hline\hline
LRESET & Local RESET, chained to the next module\\  \hline
RESET & RESET for the ancillary trigger , same as LRESET\\  \hline
ERESET & LRESET, chained from a previous module \\ 
 & The output of LRESET is the input of ERESET\\ 
 & from the previous module \\  \hline
TOUT0 & Timeout on FT \\  \hline
TOUT1 & Timeout on VAL \\  \hline
LINHIBIT & Local INHIBIT, chained to the next module\\  \hline
EINHIBIT & LINHIBIT chained from a previous module \\ 
 & The output of LINHIBIT is the input of EINHIBIT\\ 
 &  from the previous module\\  \hline
INHIBIT & INHIBIT for the ancillary trigger \\  \hline
GATE1 & FERA GATE for branch1 \\  \hline
GATE2 & FERA GATE for branch2 \\  \hline
CLR1 & FERA CLEAR for branch1 \\  \hline
CLR2 & FERA CLEAR for branch2 \\  \hline
REQ1 & FERA REQUEST for branch1 \\  \hline
REQ2 & FERA REQUEST for branch2 \\  \hline
REN1 & FERA REN for branch1 \\  \hline
REN2 & FERA REN for branch2 \\  \hline
WST1 & FERA WST for branch1 \\  \hline
WST2 & FERA WST for branch2 \\  \hline
WAK1 & FERA WAK for branch1 \\  \hline
WAK2 & FERA WAK for branch2 \\  \hline
\end{tabular}
}

{\newpage
\clearpage
\samepage \begin{tabular}{|c|c|c|c|}\hline
Name & Function \\  \hline\hline
PASS1 & FERA LAST PASS for branch1 \\  \hline
PASS2 & FERA LAST PASS for branch2 \\  \hline
FDATA1 & FERA DATA from branch1 \\  \hline
FDATA2 & FERA DATA from branch2 \\  \hline
FDATA & FERA DATA to the GIR \\  \hline
VDATA & VXI DATA from the GIR \\  \hline
EVENT-IN & EVENT NUMBER from GIR\\  \hline
EVENT-OUT & EVENT NUMBER to GIR \\  \hline
LTRESET & GIR end of readout \\  \hline
VALACK & FVI participation for the current event \\  \hline
START-READOUT & FVI data presumption \\  \hline
REN-IN & GIR ready for readout \\  \hline
DATA-READY & FVI data available \\  \hline
DATA-ACK & GIR data acknowledge \\  \hline
END-READOUT & FVI readout done \\  \hline
FTS & FAST TRIGGER in test mode \\  \hline
VALS & EUROBALL validation in test mode \\  \hline
TRIGS & ancillary TRIGGER in test mode \\  \hline
REJECTS & ancillary REJECT in test mode \\  \hline
REQS1 & FERA REQ for branch1 in test mode \\  \hline
REQS2 & FERA REQ for branch2 in test mode \\  \hline
\end{tabular}
}

{\newpage
\clearpage
\samepage \begin{figure}[h]
\centerline{\psfig{figure=dfd_manage_fera.eps}}

\label{dfd_manage_fera}
\end{figure}
}

{\newpage
\clearpage
\samepage \begin{tabular}{|c|c|c|c|}\hline
Name & Function \\  \hline\hline
DREN1 & Delayed normal REN for branch1 \\  \hline
DREN2 & Delayed normal REN for branch2 \\  \hline
WFIFO1 & write strobe for data FIFO branch1 \\  \hline
WFIFO2 & write strobe for data FIFO branch2 \\  \hline
TOUT2 & TIMEOUT on REQ1 \\  \hline
TOUT3 & TIMEOUT on REQ2 \\  \hline
HFULL1 & FIFO branch1 HALF-FULL \\  \hline
HFULL2 & FIFO branch2 HALF-FULL \\  \hline
EMPTY1 & FIFO branch1 EMPTY \\  \hline
EMPTY2 & FIFO branch2 EMPTY \\  \hline
REJECT & pileup from ancillary trigger \\  \hline
\end{tabular}
}

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\samepage \begin{figure}[h]
\centerline{\psfig{figure=legende.eps}}

\label{legende}
\end{figure}
}

{\newpage
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\samepage \begin{figure}[h]
\centerline{\psfig{figure=gate_timing.eps}}

\label{gate_timing}
\end{figure}
}

{\newpage
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\samepage \begin{figure}[h]
\centerline{\psfig{figure=res_diag.eps}}

\label{res_diag}
\end{figure}
}

{\newpage
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\samepage \begin{figure}[h]
\centerline{\psfig{figure=clear_diag.eps}}

\label{clear_diag}
\end{figure}
}

{\newpage
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\samepage \begin{figure}[h]
\centerline{\psfig{figure=inhibit_diag.eps}}

\label{inhib_diag}
\end{figure}
}

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\samepage \begin{tabular}{|c|c|c|c|}\hline
Name&Function&Access&Size(bytes)\\  \hline
LUT1&lookup table&r/w&32k\\  \hline
TIMEOUT2&Timeout on REQUEST&r/w&2\\  \hline
REN1DELAY& Delay between REQUEST and REN&r/w&2\\  \hline
GATE1DELAY& Delay between TRIG and GATE&r/w&2\\  \hline
GATE1WIDTH&Gate width&r/w&2\\  \hline
FERACTL1& FERA control&r/w&2\\  \hline
FERAFIFO1& FERA FIFO&r/w&4\\  \hline
VSN1SEL1& VSN select group 1&r/w&2 \\  \hline
VSN1SEL2& VSN select group 2&r/w&2 \\  \hline
VSN1SEL3& VSN select group 3&r/w&2 \\  \hline
VSN1SEL4& VSN select group 4&r/w&2 \\  \hline
\end{tabular}
}

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\samepage \begin{tabular}{|c|c|c|c|}\hline
Name&Function&Access&Size(bytes)\\  \hline
LUT2&lookup table&r/w&32k\\  \hline
TIMEOUT3&Timeout on REQUEST&r/w&2\\  \hline
REN2DELAY& Delay between REQUEST and REN&r/w&2\\  \hline
GATE2DELAY& Delay between TRIG and GATE&r/w&2\\  \hline
GATE2WIDTH&Gate width&r/w&2\\  \hline
FERACTL2& FERA control&r/w&2\\  \hline
FERAFIFO2& FERA FIFO&r/w&4\\  \hline
VSN2SEL1& VSN select group 1&r/w&2 \\  \hline
VSN2SEL2& VSN select group 2&r/w&2 \\  \hline
VSN2SEL3& VSN select group 3&r/w&2 \\  \hline
VSN2SEL4& VSN select group 4&r/w&2 \\  \hline
\end{tabular}
}

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\samepage \begin{tabular}{|c|c|c|c|}\hline
Name&Function&Access&Size(bytes)\\  \hline
TIMEOUT0&Timeout on Fast Trigger&r/w&2\\  \hline
FTDDELAY& Delay between Fast Trigger and FTD&r/w&2\\  \hline
FTDWIDTH& FTD width&r/w&2\\  \hline
FTCOUNT&Fast Trigger counter&r/w&4\\  \hline
TIMEOUT1&Timeout on Validation&r/w&2\\  \hline
VALDDELAY& Dealy between VALIDATION and VALD&r/w&2\\  \hline
VALDWIDTH& VALD width&r/w&2 \\  \hline
VALCOUNT& Validation counter&r/w&2 \\  \hline
TRIGCOUNT& Ancillary TRIG counter&r/w&2 \\  \hline
DIGCSEL1&Logical inspection channel select 1&r/w&2\\  \hline
DIGPSEL1&Logical inspection parameter select 1&r/w&2\\  \hline
DIGCSEL2&Logical inspection channel select 2&r/w&2\\  \hline
DIGPSEL2&Logical inspection parameter select 2&r/w&2\\  \hline
VOLTCSEL&Voltage inspection channel select&r/w&2\\  \hline
VOLTPSEL&Voltage inspection parameter select&r/w&2\\  \hline
FVICR&FVI card configuration registers&r/w&32\\  \hline
MCR&Module control register&r/w&2\\  \hline
MSR&Module status register&ronly&2\\  \hline
FTP&Simulate fast trigger pulse 250ns&wonly&2\\  \hline
VALP&Simulate validation pulse 250ns&wonly&2\\  \hline
TRIGP&Simulate ancillary trigger pulse 250ns&wonly&2\\  \hline
CFTC&Clear fast trigger counter pulse 250ns&wonly&2\\  \hline
CVALC&Clear validation counter pulse 250ns&wonly&2\\  \hline
CTRC&Clear ancillary TRIG counter pulse 250ns&wonly&2\\  \hline
\end{tabular}
}

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\samepage \begin{tabular}{|c|c|c|}\hline
Bit number&Value = 0&Value = 1\\  \hline
0&Normal mode&Test mode\\  \hline
1&Fast Trigger timeout disabled&Fast Trigger timeout enabled\\  \hline
2&Validation timeout disabled&Validation timeout enabled\\  \hline
3&Reject Off &Reject On if bit 0 set\\  \hline
4&FVI card Prom write disabled&FVI card Prom write enabled\\  \hline
5&REQ Off for FERA branch 1&REQ On for FERA branch 1 if bit 0 set\\  \hline
6&REQ Off for FERA branch 2&REQ On for FERA branch 2 if bit 0 set\\  \hline
7&No common dead time&Common dead time\\  \hline
8&Reset FVI and Ancillary trig Off&Reset FVI and Ancillary trig On\\  \hline
9&Reset GIR Off&RESET GIR On\\  \hline
10&No last card&Last card(use terminators)\\  \hline
11&Not used&not used\\  \hline
-&Not used&Not used\\  \hline
15&Not used&Not used\\  \hline
\end{tabular}
}

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\samepage \begin{tabular}{|c|c|c|}\hline
Bit number&Value = 0&Value = 1\\  \hline
0&Normal mode&Test mode\\  \hline
1&FVI FIFO branch 1 not Empty&FVI FIFO branch 1 Empty\\  \hline
2&FVI FIFO branch 2 not Empty&FVI FIFO branch 2 Empty\\  \hline
3&FVI FIFO branch 1 not Half Full&FVI FIFO branch 1 Half Full\\  \hline
4&FVI FIFO branch 2 not Half Full&FVI FIFO branch 2 Half Full\\  \hline
5&FVI FIFO branch 1 not Full&FVI FIFO branch 1 Full\\  \hline
6&FVI FIFO branch 2 not Full&FVI FIFO branch 2 Full\\  \hline
7&Inhibit is not asserted&Inhibit is asserted\\  \hline
8&Reject is not asserted&Reject is asserted\\  \hline
9&Reset GIR Off&RESET GIR On\\  \hline
10&No last card&Last card(use terminators)\\  \hline
11&Not used&not used\\  \hline
-&Not used&Not used\\  \hline
15&Not used&Not used\\  \hline
\end{tabular}
}

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\samepage \begin{tabular}{|c|c|c|}\hline
Bit number&Value = 0&Value = 1\\  \hline
0&No Clear action on ADCs&Clear action on ADCs\\  \hline
1&Sequential readout of ADCs&Random readout of ADCs\\  \hline
2&Not used&Not used\\  \hline
-&-&-\\  \hline
15&Not used&Not used\\  \hline
\end{tabular}
}

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\samepage \begin{tabular}{|c|c|}\hline
Parameter&Data value(D3-D0)\\  \hline
WST1&0000\\  \hline
REN1&0001\\  \hline
GATE1&0010\\  \hline
WST2&0011\\  \hline
REN2&0100\\  \hline
GATE2&0101\\  \hline
RESET&0110\\  \hline
INHIBIT&0111\\  \hline
REJECT&1000\\  \hline
Ancillary TRIG&1001\\  \hline
spare&1010\\  \hline
-&-\\  \hline
spare&1111\\  \hline
\end{tabular}
}

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\samepage \begin{tabular}{|c|c|}\hline
Parameter&Data value(D3-D0)\\  \hline
VCC&0000\\  \hline
GND&0001\\  \hline
VEE&0010\\  \hline
VBB&0011\\  \hline
spare&0100\\  \hline
-&-\\  \hline
spare&1111\\  \hline
\end{tabular}
}

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\samepage \begin{tabular}{|c|c|}\hline
Description&Size(byte)\\  \hline
Manufacturer ID&2\\  \hline
Card type&2\\  \hline
Serial number&2\\  \hline
Revision level&2\\  \hline
Spare&24\\  \hline
\end{tabular}
}

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\samepage \begin{figure}[h]
\centerline{\psfig{figure=overview.eps}}

\label{overview}
\end{figure}
}

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\end{document}
