GREAT 32 Channel ADC Gate routing specification.

The 32 Channel ADC card accepts one Gate per channel. There are requirements for one Gate to cause conversions in more than one channel.

Each channel is controlled by a Gate mode select register, and as a member of a group of eight channels, by a group mode select register.

The logic to route the Gate signals is programmed into a high speed Altera EPLD. While it will be possible to make special cases for routing logic, it is not currently a design target to allow the user to program this for each experiment.

The modes that are available to each channel are listed and explained in the following paragraphs. If there are changes, or further modes required, please let me know at p.j.coleman-smith@dl.ac.uk.

Note: G_n = the Gate input for channel ‘n’.

# = Logic OR.

0 : No routing.

The channel is only triggered by its own Gate.

Gate to ADC_n = G_n.

1: Nearest Neighbour.

Each channel is triggered by its own Gate, or by the any of the nearest four channels.

The mode select register contains four enable bits to select which of the neighbouring channels are able to trigger this channel. This method allows for maximum use of channels at the edge of strip detectors. Channels 0, 1, 30, and 31 are routed to adjacent ADC modules to allow detectors to be instrumented across module boundaries.

Gate to ADC_n = G_n # G_(n-1) & Enb₁ # G_(n-2) & Enb₂ # G_(n+1) & Enb₃ # G_(n+2) & Enb₄.

2:Group Member, Any of the Group, triggers all.

Every channel of the group, which is selected for this mode, will be triggered by any of the eight Gates.

A Group mode register will contain a mask to disable selected channels for this mode.

Trigger = G_g0 & Enb₀ # G_g1 & Enb₁ # G_g2 & Enb₂ # G_g3& Enb₃ # G_g4& Enb₄ # G_g5& Enb₅ # G_g6& Enb₆ # G_g7& Enb₇

3:Group Member, One of Group, triggers all.

Every channel of the group, which is selected for this mode, will be triggered by one of the eight Gates.

A Group mode register will select the Trigger Gate.

Trigger = G_gT.