This proposal reduces the GREAT data word size from 48 bits to 32 bits. It is further proposed that this format is used in the interface between the Event collector, and the Event Sorter.
The information that is lost in this change is the top 20 bits of the timestamp. There is a SYNC information event, transmitted from each ADC module every 655uS, which consists of all 48 bits of the Timestamp. The Timestamp sent with every event consists of 28 bits ( 228 => 2.7 seconds ), this overlaps with 4096 SYNC pulses. The probability of a data error in the time being undetected is very small.
The flow control between the ADC card and the SHARC require particular types of timestamp to be transmitted from the ADC to indicate the Pause, and Resume states of the ADC card.
The following format is proposed to meet these existing requirements, and to allow future flexibility.
Addition of a data structure to handle ADC Sample Buffers from the SAGE/LISA LyrTech modules.
Addition of information word to handle TimeStamp information from
SAGE/LISA LyrTech Modules. This is similar to the SYNC100 TimeStamp
except that the information originates within the LyrTech ADC module
firmware and will not have the same strict periodic nature as the
SYNC100 information. Data within an output stream can however be
assumed to be time ordered.
Note that while all data items occupy 64 bits and hence are aligned on a 64 bit boundary they are generated as 2 32 bit data words. This is important when considering byte ordering.
Add layout of bits within Channel Ident field. Add Sequence Number Information Item.
Add additional Information Codes.
Additions for use with Aida (FEE64 modules).
Additions for use with at GSI with MBS (Aida).
Add support for R3B.
Add note regards White Rabbit 64 bit timestamp.
Add additional Information Items used by R3B (Silicon Tracker) & White Rabbit.
Add format for use with CAEN Digitizers.
Add format for use with Miniball (FEBEX4 modules) .
Update format for use with Miniball (FEBEX4 modules) .
All data items are 64 bits handled as two 32 bit words. These two words are formatted as follows.
| Bit Position |
31 | 30 | 29 | 28 | 27 to 16 | 15 to 0 | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Field Value |
1 | 1 | Fail | Veto | Channel Ident | ADC data | ||||||||
| Bit Position |
31 to 28 | 27 to 0 | ||||||||||||
| Field Value |
0 | Time Stamp 27:0 | ||||||||||||
For the Aida fee64 module the Fail bit is currently not used. Will be 0.
The Veto bit (bit 28) will contain the ADC Range setting: (0 = low; 1 = high).
For FEBEX ADCs (Miniball) bit 29 contains Pile Up indication. Bit 28 is unused. See FEBEX Data Item Format.
For R3B data the ADC data occupies 12 bits which enables support for the 4K channels per module. These two words are formatted as follows.
| Bit Position |
31 | 30 | 29 | 28 to 12 | 11 to 0 | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Field Value |
1 | 1 | Hit | Channel Ident | ADC data | |||||||||
| Bit Position |
31 to 28 | 27 to 0 | ||||||||||||
| Field Value |
0 | Time Stamp 27:0 | ||||||||||||
For the R3B 4K module the Hit bit is set to 1.
For CAEN data the ADC data occupies 16 bits and bit 28 is used by the Channel Ident. These two words are formatted as follows.
| Bit Position |
31 | 30 | 29 | 28 to 16 | 15 to 0 | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Field Value |
1 | 1 | 0 | Channel Ident | ADC data | |||||||||
| Bit Position |
31 to 28 | 27 to 0 | ||||||||||||
| Field Value |
0 | Time Stamp 27:0 | ||||||||||||
The Lyrtech digitial ADCs, Aida FEE64 modules and CAEN ADCs may also generate a data buffer containing the ADC sample data. This is sent as a 64 bit header in two 32 bit words followed by n samples where each sample is a 16 bit data item. These words are formatted as follows.
| Bit Position |
31 | 30 | 29 | 28 | 27 to 16 | 15 to 0 | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Field Value |
0 | 1 | 0 | 0 | Channel Ident | Sample Length | ||||||||
| Bit Position |
31 to 28 | 27 to 0 | ||||||||||||
| Field Value |
0 | Time Stamp 27:0 | ||||||||||||
Note: In the case of CAEN ADCs bit 28 is a part of the Channel Ident field
The "Sample Length" defines the number of 14 bit sample data items following and will be a multiple of 4.
These data items follow in the following format.
| Field Value |
0 | 0 | Sample n (14 bits) | 0 | 0 | Sample n+1 (14 bits) | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Field Value |
0 | 0 | Sample n+2 (14 bits) | 0 | 0 | Sample n+3 (14 bits) | ||||||||
Note that for normal data the 2 most significant bits of each 16 bit sample word will be zero. However the header does contain the number of samples. This should be used when processing the data since for diagnostic purposes the raw data from the hardware may be passed by this path and this may contain data in which the 2 most significant bits are used. This diagnostic information is likely to be removed before the data stream is written to final storage.
| Bit Position |
11 | 10 to 5 | 4 to 0 |
|---|---|---|---|
| Field Value |
0 | VXI Module Number | ADC Number |
| Bit Position |
11 | 10 to 5 | 4 | 3 to 0 |
|---|---|---|---|---|
| Field Value |
0 | VHSADC Module Number | 0=energy; 1=baseline | ADC Number |
| Bit Position |
11 | 10 to 5 | 4 | 3 to 0 |
|---|---|---|---|---|
| Field Value |
0 | VHSADC Module Number | 0=trace data; 1=raw data | ADC Number |
| Bit Position |
11 to 6 | 5 to 0 |
|---|---|---|
| Field Value |
FEE64 Module Number | Channel Number |
| Bit Position |
16 to 11 | 10 to 7 | 6 to 0 |
|---|---|---|---|
| Field Value |
R3B Module ID (0=>0x3f) | R3B ASIC Number (0=>15) | Channel Number (0=>127) |
| Bit Position |
12 to 8 | 7 to 6 | 5 to 0 |
|---|---|---|---|
| Field Value |
CAEN Module ID (0=>31) | Data Id (0=>3) | Channel Number (0=>63) |
The Data Id will be dependent on the particular CAEN module and firmware option.
PHA =0 energy; =2 baseline; = 3 fine timing
PSD =0 Qlong; =1 Qshort; =2 baseline; = 3 fine timing
| Bit Position |
11 to 10 | 9 to 6 | 5 to 4 | 3 to 0 |
|---|---|---|---|---|
| Field Value |
SFP Id (0=>3) | Board Id (0=>15) | Data Id (0=>3) | Channel Number (0=>15) |
The Data Id will be dependent on the particular firmware option.
fast mode readout:
=0 16 bit integer bined energy
=1 16 bit integer time difference since previous data group
=2 32 bit integer (low 16 bits); =3 32 bit integer (high 16 bits)
standard mode readout:
=0 16 bit integer waveform array
See ADC Data Format: Bit 29 contains the Pile Up bit.
See Info fields code 14 & 15 for the Global Trigger items. Module Number is the 6 bits SFP Id + Board Id.
| Bit Position |
31 | 30 | 29 to 24 | 23 to 20 | 19 to 0 | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Field Value |
1 | 0 | Module Number | Information Code | Information Field | |||||||||
| Bit Position |
31 to 28 | 27 to 0 | ||||||||||||
| Field Value |
0 | Time Stamp 27:0 | ||||||||||||
The Module number identifies the source of the information. This will be an ADC VXI card, Lyrtech ADC module or FEE64 module.
Information code will be able to identify one of 16 possible information words. The information Field is defined for each of the codes.
| Information Type | Code | Information Field Definition |
|---|---|---|
| Undefined Data | 0 | |
| ADC Channel Pile-Up | 1 | Channel Number |
| Pause TimeStamp | 2 | Timestamp bits 47:28 |
| Resume TimeStamp | 3 | Timestamp bits 47:28 |
| SYNC100 TimeStamp | 4 | Timestamp bits 47:28 |
| White Rabbit TimeStamp Marker | 4 | Timestamp bits 47:28 |
| White Rabbit TimeStamp Marker | 5 | Timestamp bits 63:48 |
| Aida FEE64 discriminator data | 6 | FEE64 discriminator data |
| Extended Item TimeStamp | 7 | Timestamp bits 47:28 |
| Scanning Table Information | 8 | information index (16-19) + data (0-15) |
| AIDA Correlation scaler | 8 |
information index (16-19) + data (0-15) index=0 data=scaler (0-15) index=1 data=scaler (16-31) index=2 data=scaler (32-47) |
| Silicon Tracker Time Correction | 7 | Timestamp bits 47:28 |
| Silicon Tracker Time Correction | 8 | Timestamp bits 63:48 |
| ADC Channel/Energy Over-Range | 9 | Channel Number |
| ADC Channel/Energy Under-Range | 10 | Channel Number |
| ADC Channel Overflow | 11 | Channel Number |
| ADC Channel Underflow | 12 | Channel Number |
| Trigger Sequence Number (event number) | 13 | module sequence number |
| External Data (R3B Master Trigger) | 14 | Timestamp bits 47:28 |
| External Data (R3B Master Trigger) | 15 | Timestamp bits 63:48 |
| External Data (FEBEX/MiniBall Global Trigger) | 14 | Timestamp bits 47:28 |
| External Data (FEBEX/MiniBall Global Trigger) | 15 | Timestamp bits 55:48 |
| Data Link Statistics | 14 | Link Number. Transfer between Sender and Receiver. Timestamp is replaced by a buffer count |
| SHARC Link number | 15 | Link Number. Transfer between SHARC and Receiver. Timestamp is replaced by a buffer count |