GREAT VXI Slot 1 interface

P.J.Coleman-Smith  Updated last: 3rd November 2004

 

Introduction

The module provides an interface for the VXI Backplane  TTLTRG, ECLTRG, and Local Bus lines as defined for the obsolete STR8032 Resource Manager in the document EDOC035. The front panel interface is connected to the Master Trigger in the same way as the STR8032 using two flat ribbon cables ( 40 way from Trigger to RM; 14 way from RM to Trigger ).

The module provides a VME slave interface for software monitoring and control of the lines. A VME interrupt may be generated from the change of state of one of the TTLTRG lines.

The following VXI bus signals are buffered from the VXI backplane to the front panel for monitoring purposes. The Monitoring signals are differential ECL on a 16-pin IDC connector.

 

VXI bus signal

Front panel signal

CLK100

100Mhz Clock

SYNC100

Timestamp synchronisation pulse

STARX

Timestamp reset pulse or Fast Trigger

 

The module is a ‘D’ size VXI module.

 

 

VME Slave.

The VME slave is located in the A16 configuration register area. The module is a register based module. The module is capable of Dynamic only configuration. The module is an interrupter.

 

 

Interface definition. (from EDOC035)

Signals are all Logic levels unless described otherwise.

1.      Local Bus

These are connected to both LBUS A, and LBUS C  to allow the slot 1 card to be used in any slot .

 

·         LBUS0 Supplementary analogue sumbus 1 . Analogue. buffer to a front panel LEMO00.

·         LBUS1 Supplementary analogue sumbus 2 . Analogue. buffer to a front panel LEMO00.

·         LBUS2 Analogue inspection line 1. Analogue. Front panel LEMO00.

·         LBUS3 Analogue inspection line 2. Analogue. Front panel LEMO00.

·         LBUSA4 RENin LBUSC4 RENout (Readout ENable daisy chain). This is set/cleared from a register in the VME slave. It is for signalling VME readout by a processor.

·         LBUS5 Voltage inspection line  Analogue. Front panel LEMO00.

·         LBUS6 Controle des fenetres Analogue. Front panel LEMO00.

·         LBUS7 not allocated

·         LBUS8 Event Number bit 1.

·         LBUS9 Event Number bit 2.

·         LBUS10 Event Number bit 4.

·         LBUS11 Event Number bit 8.

·         LBUS12 Reserved (Anti­Compton veto in Eurogam)

·         LBUS13 Reserved (Anti­Compton veto in Eurogam)

·         LBUS14 Reserved (Anti­Compton veto in Eurogam)

·         LBUS15 Reserved (Anti­Compton veto in Eurogam)

·         LBUS16 Reserved (Anti­Compton veto in Eurogam)

·         LBUS17 Reserved (Anti­Compton veto in Eurogam)

·         LBUS18­35 not allocated.

2.      ECLTRG 0­5

·         ECLTRG0 Validation 1

·         ECLTRG1 Synchronisation of triggers for test mode.

·         ECLTRG2 Inhibit Request

·         ECLTRG3 Logic inspection line 1. Front panel LEMO00 Fast NIM.

·         ECLTRG4 Logic inspection line 2. Front Panel LEMO00 Fast NIM.

·         ECLTRG5 Validation 2

 

3.      TTLTRG 0­7

All the following TTL trigger lines have common buffering through the Slot 1.

·         TTLTRG0 End of coding

·         TTLTRG1 End of readout

·         TTLTRG2 Transfer all scalers to shadow registers.

·         TTLTRG3 Clear

·         TTLTRG4 Go/Stop.

·         TTLTRG5 Event reject.

·         TTLTRG6 Validation 3 .

·         TTLTRG7 Inhibit Action.

4.      Sumbus

SUMBUS.

Buffer to a front panel LEMO00.

Register definitions

1.      VXI Dynamic configuration Registers.

These are as required for a VXI A16 register based interrupter.

Offset 0 :        Read : ID

                        Write: Logical Address.

Offset 2:         Read : Device type.

Offset 4:         Read: config status

                                        Bit 2 : Passed.

                                        Bit 3 : Ready.

                                        Bit 14 : MODID*

                        Write: config control

                                        Bit 0: Reset module !

                                        Bit 1: Sysfail Inhibit.

 

2.      Interface Control/Status

Offset 0x20 : Read/Write.

Bit 0: RENO           Enable the RENO to the next module.

Bit 1: Enable Slot1 controlled  LBUS and TTLTRG and ECLTRG lines.

Bit 2: VXI Go. ( TTLTRG4 ).

Bit 3: Inhibit Request.          (ECLTRG 2 )

Bit 4: Transfer Scalers ( TTLTRG2 )

Bit 5: Enable TTLTRG lines from the Front Panel 40-way connector to the backplane

Bits 6 => 15 permanently 0.

3.      Interface status

Offset 0x22 : Read only.

 

NOTE: TRG lines are displayed logic 1  = True. ( TTLTRGs are inverted from the backplane )

0

TTLTRG 0

Coding

1

TTLTRG 1

Readout ( BLTACK*)

2

TTLTRG 2

Transfer Scalers.

3

TTLTRG 3

Clear  ( RAZ )

4

TTLTRG 4

Go

5

TTLTRG 5

Event Reject

6

TTLTRG 6

Validation 3

7

TTLTRG 7

Inhibit Action

8

ECLTRG 0

Validation 1

9

ECLTRG 1

Synchronise Trigger

10

ECLTRG 2

Inhibit Request

11

ECLTRG 3

Logic Inspection 0

12

ECLTRG 4

Logic Inspection 1

13

ECLTRG 5

Validation 2

14

Interrupt

Interrupt is present in this module.

15

ADC Busy

The Voltage Inspection ADC is busy

4.      Interrupt control

Offset 0x24 : Read/Write.

The interrupter is an ROAK. That is the interrupt is reset by the Interrupt Handler’s acknowledge cycle.

Bits 7 => 0                             Interrupt Vector.

Bit 10 => 8                             IRQ select. Choose the IRQ line to drive.

Bit 15 => 11                           Not used. Registered bits.

5.      Interrupt Select

Offset 0x26: Read/Write.

Bits 3 => 0                             Interrupt source selected from Interface Status register by bit number.

Bit 4 Interrupt method            0 => Edge triggered.

                                                   1 => Level Triggered.

 

Bit 5 Edge select.                     0 => Positive. ( Goes True )

                                                   1 => Negative. ( Goes False )

 

Bit 6 Level select.    0 => Active.

                                                   1 => Inactive.

 

Bit 7 Interrupt Enable.            0 => Disable Interrupt.

                                                   1 => Enable Interrupt.

 

6.       ADC Data

Offset 0x28: Read/Write.

Write starts a conversion.

Read ADC data on bits 0 => 15.

 

 

 

Front Panel

 

 

 

 

 

                           VXI Sumbus

 

                  Logic Inspection 0

 

            Analogue Inspection 0

 

                                Sumbus 0

 

                  Voltage Inspection

 

 

 

 

Coding, Readout, Inhibit Request 14-way cable from previous Interface.

 

 

 

40-Way Trigger signals from the Master Trigger.

 

 

 

 

 

 

GREAT Timing monitor. Clock100, Sync100, STARX

 

 
 

 

 

 

 

 

 

 

Logic Inspection 1

 

Analogue Inspection 1

 

Sumbus 1

 

Controle Des Fenetres

 

 

 

 

Coding, Readout, Inhibit Request 14-way cable to Master Trigger

 

 

 

 

40-Way Trigger signals Output to next Interface.