1 Euroball Trigger User Guide Draft v0.1 (December 1997) Written by Ian Lazarus 1 1.0 Introduction The main function of the trigger card is to generate the 2 global trigger signals known as Fast Trigger (FT) and Validation (Val). The details of the Euroball Trigger system are described in ÒAn Introduction to the Euroball ElectronicsÓ with which the user is assumed to be familiar. Associated with the Val pulse is a 32 bit event number which is incremented at the end of every Val pulse. The bottom 4 bits of this event number are used by the rest of the system as a synchronisation reference. The event number may be read from the trigger card in the event by event data. The decision as to whether or not to generate FT and Val pulses is made by a reconfigurable logic cell array (LCA) implemented in a Xilinx 4013 LCA. This LCA is known as the FTV_LCA. The inputs to the FTV_LCA are a mixture of system signals and physics signals. The system signals indicate whether or not the system is already busy (dead) and whether the system is in the Stop state or the Go state. If the system is not dead and is in the Go state then the physics inputs are compared against the programmed criteria for FT and Val generation. The physics inputs come from 4 sumbuses (for fold selection) and 8 logic inputs (for signals from ancillary detectors or beam state indicators). The FTV_LCA initially loads a default program from its PROM which will handle most experiments. For unusual experimental trigger conditions the FTV_LCA can be reconfigured by downloading a new configuration file from a library in the Euroball MIDAS control software. 2.0 Physics Inputs for FT and Val decisions The MIDAS control window for the Trigger card controls all the physics inputs from which FT and Val generation is controlled. 2.1 Sumbus inputs The 4 sumbus inputs allow selection based on fold. The 4 sumbus inputs are electrically identical. The inputs should be connected to current sources generating 4mA per hit with an operating limit of about 80mA total current (fold=20). The Cluster Ge cards and Eurogam Ge electronics generate this level normally. The MIDAS threshold calibration assumes these input levels when it maps the fold selection to a real DAC output. (See table in appendix 1 for DAC settings.) Conventionally sumbus 1 is connected to RawGe multiplicity, sumbus 2 to clean Ge multiplicity leaving sumbus 3 and sumbus 4 available for signals from ancillary detectors (or as spares in case of problems with sumbus 1 and 2). The sumbuses are electrically identical and differ only in the number of simultaneous threshold checks which may be performed. Each sumbus is connected to a number of leading edge discriminators which check its level against the DAC output level set by the userÕs fold selection. The discriminator outputs are connected directly to the trigger logic FTV_LCA and also to non-retriggerable Gate and Delay modules. The Gate and Delay outputs are also connected to the trigger logic FTV_LCA, permitting the use of delayed or stretched pulses where coincidence with external devices or signals is required as a trigger condition. The sumbus inputs are controlled from the part of the MIDAS window at the top, under the ÒsumbusÓ pull down menu button. Use the pull down menu to select one of the 4 sumbuses and then the 12 sliders below will control the selected sumbus. The MIDAS software shows the user only one sumbus at a time. The user can control the following: 1) Sumbus enable/disable for the current sumbus 2) Fold selection threshold (³n) by using the threshold slider 3) Delay and Width of Gate and Delay output using the appropriate sliders. Note that sumbus 1 has four different discriminators allowing up to 4 different fold selections to be used simultaneously with various other inputs when making complex FT selections (see example in 2.3). Each discriminator has an associated Gate and Delay module. Sumbus 2 has 3 discriminators, sumbus 3 has 2 discriminators and sumbus 4 has only 1 discriminator. Unused sliders for sumbus 2, 3 and 4 are inactive and Ògreyed outÓ. Each sumbus produces a buffered voltage signal at the triggerÕs front panel proportional to the current on the sumbus. Sumbus 1 has an additional feature where a fast NIM pulse is available on the front panel connected to the output of one of the four discriminators. This selection is made by a pull down menu at top of the MIDAS control screen. 2.2 Logic inputs The logic inputs are controlled from the part of the MIDAS window immediately below the ÒLogic InputÓ pull down menu button. Use the pull down menu to select one of the 8 logic inputs and then the 3 sliders below will control the selected input. The 8 front panel logic inputs are each connected to a leading edge discriminator with its own programmable threshold with a range +2volts to -3v. This is adjusted using the slider called ÒthresholdÓ. Inputs 1 to 4 have a gate and delay generator for time alignment. The delay and width are controlled from the appropriate sliders. Unused sliders for delay and width of inputs 5-8 are inactive and Ògreyed outÓ; only the threshold may be adjusted for inputs 5-8. In the prototype card the logic inputs are always enabled so may only be disabled by use of the threshold. For the production Trigger card an enable button will be added to enable or disable all logic inputs (ticked= enabled). 2.3 Example of a complex Fast Trigger Condition In most experiments the simple default program described in 4.0 will be sufficient, but to demonstrate the power of the trigger system here is a more complex example. In this example we look for 7 trigger conditions simultaneously, based on the folds detected on sumbus 1, sumbus 2 and sumbus 4 and pulses from 6 different logic inputs. There is a global requirement that in addition to the 7 trigger conditions, also the fold seen on sumbus 3 must be within a specified range (2 to 9). FT = (SB3Fold³2 AND NOT_SB3Fold³10) AND ( (SB1Fold ³5) OR (SB1Fold³3 AND LogicInput 1) OR (SB1Fold ³2 AND LogicInput 2) OR (SB1Fold³1 AND LogicInput 3 AND NOT_LogicInput 4) OR (LogicInput 6) OR (SB1Fold³3 AND SB2Fold³2) OR (SB4Fold³7 AND LogicInput 7) ) Each of the 7 lines may be allocated a different bit in the Trigger Type field, so that they can be differentiated at the time of the validation for 7 different validation checks. There is no real limit to the number of OR terms or AND terms which can be specified although practically the setup and time alignment will be the limiting factor, and only 8 different trigger type bits exist without coding and decoding the 8 bit trigger type field. The FT that results from these conditions must arrive at the Ge and BGO channels at approximately the same time whichever condition generates it. In this way the FT sample coincides with an FT pulse for a good event. The FT pulse width must be wide enough to cover all possible jitter between conditions. The input gate and delays must be used to delay the fastest conditions to wait for the slowest input. The gate and delays can also be used to determine which input acts as a gate for which other (for example a wide logic input ANDed with a Fold³n condition will be timed by the Ge, whereas a wide pulse derived from the Fold³n ANDed with a narrow pulse from an ancillary detector via a logic input will be timed by the ancillary detector. All inputs are available on inspection lines (see 8.0) to facilitate setup of complex triggers. 3.0 System Inputs for FT and Val decisions The VXI GO bit must be set to GO (i.e. the system must be running) before any triggers will be generated. 3.1 Definition of Busy (Triggers Blocked) In parallel mode the Inhibit Action signal is set for a period controlled by the ÒInhibitÓ slider. During this time the trigger is busy. In Common dead time operation, the Inhibit Action slider must be adjusted to cover at least the time from Fast Trigger to the start of readout. The Trigger is also blocked while the Readout* signal on the 14 way input cable is true, indicating that at least one VXI crate is still reading data into its STR8080 buffer. During this time the trigger is busy. In both parallel and common dead time, the Inhibit Request input prevents the generation of any further Fast Triggers and validations. However if InhReq is asserted after FT and before Val, it does not prevent the validation for the event during which it is asserted. 4.0 Output pulses Using the inputs described in section 2, triggers may be generated. The default LCA program will generate a Fast Trigger when: (Sumbus 1 threshold 1 exceeded) OR (Sumbus 2 threshold 1 exceeded) OR (Sumbus 1 threshold 1 exceeded AND FP logic input 1 is true) OR (Sumbus 3 threshold 1 exceeded) OR (Sumbus 4 threshold 1 exceeded) AND the card is not busy (indicated by Inhibit Action being set). 4.1 Fast Trigger The internal Fast Trigger signal from the FTV_LCA is generated when the FT condition described above is satisfied. The FT output of the FTV_LCA is gated with an optional Tref (Time reference, for example RF pulses or inner ball) and then triggers a gate and delay generator to make the Fast Trigger pulse whose delay and width are defined by the sliders marked ÒFast TriggerÓ. When the Tref Enable button is ticked, a fast NIM pulse (or level) must be provided on the Tref input whenever a Fast Trigger is required. When the Tref button is not enabled, the Trigger card itself provides an active level to simulate a permanently true Tref. The output of the FTV_LCA which triggers the FT gate and delay will also trigger the gate and delays called ÒInhibitÓ (defining system dead time in parallel mode) and ÒVal-GateÓ defining the delay and width of the Validation Gate signal. There are sliders to control these delay and width settings. 4.2 Validation During the Validation Gate signal the Validation logic condition is checked. The default setting is to validate every event, but the user may download a new trigger LCA setting from the library to introduce a validation logic condition, for example using a logic input from an ancillary detector. The Validation output is generated when the Validation trigger condition (default - Validation Gate) is true and triggers the gate and delay generator controlled by the ÒValidationÓ sliders. Users should consider carefully the efficiency of their validating device if they introduce a validation condition. An example is given in Appendix B. 5.0 TAC The Trigger card contains a TAC for use during experiments. It can be started by one of 4 signals (Front panel TAC Start, Sumbus 1 discriminator 1, Sumbus 2 discriminator 1, or Logic input 1). It can be stopped by one of 4 signals (Front panel TAC Stop, Sumbus 1 discriminator 1, Sumbus 2 discriminator 1, or Logic input 1). The start and stop signals are selected from pull down menus in the area of the window called ÒTAC ControlsÓ. The TAC must be enabled by clicking the TAC enable. Note that the ADC requires 2.7µs after TAC stop to convert its data, so you should delay the start of readout (back of Validation) until the ADC is not busy by either delaying or making wider the validation output. If you read too soon then you will read the previous eventÕs data. The ADC is a 12 bit ADC without sliding scale. TAC range is 2µs. 6.0 Readout of data The trigger card provides up to 8 data parameters, each enabled or disabled under user control. The area of the window called ÒReadout ParametersÓ contains buttons to enable (when ticked) or disable the readout of the following parameters: ¥ Event number bottom 16 bits ¥ Event number top 16 bits ¥ Pattern/trigger type (from trigger selection LCA) ¥ TAC output ¥ Sumbus level from sumbus 1-4 The event number is incremented at the back edge of every validation pulse, but the event number that is to be read is latched at the start or the validation pulse. The pattern or trigger type parameter is useful when several trigger conditions are in use simultaneously so that different validation conditions can be used for different trigger types. The sumbus level is coded by peak sensing ADCs where 13 decimal corresponds to fold=1, 26 decimal is fold=2 etc.. 7.0 Scalers 8 scalers are provided and connected to the following signals: 1 = Fast Trigger Request (trigger condition) 1 2 = Fast Trigger Request (trigger condition) 2 3 = Fast Trigger Request (trigger condition) 3 4 = Fast Trigger Request (trigger condition) 4 5 = Fast Trigger out 6 = Validation out 7 = Readout cycles 8 = user defined The scalers are displayed and controlled in the bottom right corner of the trigger window. There are 2 buttons for each scaler. The left button enables the scaler when ticked and the right button is a status indicator for 32 bit overflow. All scalers will be cleared by the clear button. Pressing the update button displays either the current total counts or the current rate (measured over a 3 second period) depending on the status of the Counts/Rates toggle buttons (yellow=selected, blue = not selected). Scalers cannot be included in the event by event data stream. 8.0 Inspection Points Inspection lines are provided for many internal signals and are controlled from the 5 pull down menus near the bottom of the card. There are 2 digital inspection lines and 2 analogue inspection lines and also a voltage inspection line. 9.0 Reloading the LCA To reload the FTV_LCA which searched for the trigger condition, press the ÒLoad LCAsÓ button at the bottom of the window in the middle. This will bring up a new frame in which you must select the program you want to load and then click on the load button. The frame will disappear after a successful load. There is a status bar on the main trigger window which is called ÒCurrent LCA ProgramÓ. 10.0 ÒThe Trigger DoesnÕt workÓ Some common mistakes: If there are no FT outputs from the trigger then the most likely cause it that you have set it up wrong! Here are some things to check: 1) Is VXI GO set? (look at the system control window) 2) Is Inhibit Request set (look at the Resource Manager window, selecting the resource manager for the VXI crate where the trigger is located) 3) Are the Ge CFDs enabled? (look for pulses on sumbus on trigger analogue inspection lines) 4) Are the trigger sumbus discriminators enabled? (select the correct sumbus with the pull down menu and check the ÒSumbus enableÓ tick box.) 5) If the sumbus discriminator is enabled and the sumbus input pulse can be seen then look for the discriminator output on the inspection line. If there is no output then check your sumbus threshold setting and adjust it until there is an output. 5) Look at the timing of the signals in your trigger equation: do the signals for any AND conditions overlap when viewed on the inspection lines? 6) Check the Tref button. If you tick Tref then you must provide a fast NIM pulse (or active level) during the internal FT pulse in order to trigger the FT output gate and delay. If you get extra triggers then check the hidden sumbuses and logic inputs by looking at each part of the pull-down menu in turn. Unused sumbuses should be disabled and unused discriminators should be set to their default full scale value (fold³23). Appendix A Trigger fold settings input voltage sb1comp1 fires up to DAC=nn equivalent fold suggested DAC value (decimal) -100mV up to 8 ²1 6 -200mV up to 20 ²2 17 -300mV up to 31 ²3 28 -400mV up to 43 ²4 40 -500mV up to 54 ²5 51 -600mV up to 67 ²6 64 -700mV up to 78 ²7 75 -800mV up to 89 ²8 86 -900mV up to 102 ²9 99 -1000mV up to 113 ²10 110 -1100mV up to 125 ²11 122 -1200mV up to 136 ²12 133 -1300mV up to 148 ²13 145 -1400mV up to 159 ²14 156 -1500mV up to 170 ²15 167 Appendix B Validation Efficiency With a low efficiency device then the system will spend a large percentage of its time waiting for validations that never come. For example consider a trigger condition of gamma-fold²2 validated by a 10% efficient ion detector which produces a signal 5µs after the gamma rays are detected. In this case we would require a ValGate delay of 4.5µs and ValGate width of 1µs. So the system would trigger at a rate determined by the gamma-fold²2 (for example= 50kHz) and receive good validations at a rate of 5kHz. At a rate of 5kHz the system is dead for about 15µs including readout for a good event. At a rate of 45kHz the system is dead for 5.5µs waiting for validations that never come. So dead time = 7.5% for good events and 24.75% for failed validations, total 32.25% dead time.