FERA readout

On completion of the coding sequence the REQ signal is received from each FERA branch. On receipt of REQ on one FERA branch, the FVI must assert the REN with an adjustable delay between 0 and 50 Sec, 100 nSec steps. A timeout checks the arrival of REQ for each FERA branch. If a timeout occurs, the REN is asserted and the readout sequence is started on the fera branch.
When the FERA WST is received from each branch, the FVI must :

1. convert the data to the EUROBALL format.
2. store the converted data into a FIFO.
3. send WAK to the FERA branch.

this sequence is repeated until the (last) PASS from every FERA branch is received. There is one FIFO per FERA branch. When PASS is received from the two branches, all the FERA ADCs connected to the FVI are read and the FVI must :

1. Wait for GIR readout completion (else because the GIR FIFO is empty or the FVI data FIFOs are empties; this choice is done by the logic which drives the GIR readout). Then the FVI can deassert its local INHIBIT and the INHIBIT sent to the ancillary trigger if the bit CDT is not set in the control register (see section registers). If the CDT bit is set, the INHIBIT sent to the ancillary trigger will remain set until every INHIBIT from every FVI will be cleared. When INHIBIT sent to the ancillary trigger is cleared a new coding sequence can be launched when TRIG is received.
2. If during the FERA readout one FIFO is HALF-FULL, the INHIBIT remains true to prevent data loss until The FIFO is EMPTY.