When the ancillary trigger detects a raw particule (RAW PARTICULE), it send it to the Master trigger and start the ancillary trigger signal (TRIG) in coincidence with the Raw Ge signal from the Master trigger. Depending of somes delays, the Fast Trigger sent by the master trigger (FT) can be received either before the ancillary trigger (TRIG) or after. Depending of the experiment conditions, the master trigger can or not send a validation (VAL). When TRIG is asserted, the FVI must start the FERA coding (GATE).
During all the FERA coding and FERA readout, the FVI asserts INHIBIT.
2 timeouts check the arrival of VAL and FT. These timeout can be turned ON or OFF. If one timeout occurs, the FVI clears all the FERA ADCs
When the FVI receives FT it sends FTD to the ancillary trigger with adjustable delay and width.
When the FVI receives VAL it sends VALD to the ancillary trigger with adjustable delay and width.
When the ancillary trigger detects a pileup during the FERA coding, it asserts REJECT, then the FVI must clear all the FERA ADCs. If REJECT is asserted after the FERA coding, the event is good and the readout is normally performed.
On completion of the coding and FERA readout sequence (normal or ended by a timeout, the FVI sets RESET.