\documentstyle[11pt,a4wide]{article} \title{ ROCO Card Register Layout Specification} \author{This document is aggreeded by J.L. PEDROZA.} \date{7 october 1991} \begin{document} \begin{titlepage} { \hoffset=1truein \hsize=5.25truein \vsize=10.25truein \font\small=cmssbx10 at 14.4truept \font\medium=cmssbx10 at 17.28truept \font\large=cmssbx10 at 20.74truept \hrule height 0pt \parindent=0pt %\parskip=0pt \hskip 3.9truein \large EDOC132\par \vskip .5truein \large EUROGAM PROJECT\par \vskip 1.5truein \hrule height 2pt \vskip 20pt \medium EUROGAM DATA ACQUISITION SYSTEM\par \vskip .5truein ROCO Card Register Layout Specification\par \vskip 20pt \hrule height 2pt \vskip 1truein \medium Edition 1.0\par \vskip 5pt Last Register Layout Revision:\par February 26, 1992\par \vfill \medium P.Kadionik \vskip 5pt CENBG Bordeaux\par \vskip 5pt CNRS-IN2P3 France\par } \end{titlepage} \maketitle \noindent This document has been written by P. Kadionik (CENBG) from the reference document :\\ EDOC077, ROCO VXI Unit Specifications by J.L. Pedroza.\\ Here is the list of Controlable Parameters :\\ \section{Controlable Parameters :} {\bf VXI standard registers (VXI norme 1.3) :} \begin{itemize} \item ManID register : 16 bits [rw] \item Device type/Model code : 16 bits [r] \item Status/Control register : 16 bits [rw] \item Offset register : 16 bits (unused) \end{itemize} {\bf VXI user specified registers :} \begin{itemize} \item Serial number register : 16 bits [r] \item Modification level register : 16 bits [r] \end{itemize} {\bf VXI device dependant registers :} \begin{itemize} \item Endsubevent register : 32 bits [rw] \item ROCO control/status register : 16 bits [rw] \item Word count register : not accessible via the VME bus \item Data fifo test register : 32 bits [w] \item Event number test register : 4 bits [w] \item Event number register : not accessible via the VME bus \item Time outs register : 16 bits [w] \item Interrupt/bus request register : 8 bits [w] \end{itemize} \section{Address space allocation :} \begin{itemize} \item 000-03F Module parameters \end{itemize} The ROCO card is a A16 VXI "register based" device.\\ The VXI A16 base address of the ROCO card is fixed by the VXI autoconfiguration software.\\ \section{Register layout :} \noindent Note : bits fields or bits without label are undefined or unused.\\ \vbox{ \begin{verbatim} Name: VXI ID Register Offset: @0000 read/write 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | Logical Address | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |Dev Typ|Add Spa| Manufacturer ID | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Add Spa = 0x3 : Address Space is A16 only Dev Typ = 0x3 : Device Type is "register based" device \end{verbatim} } \vbox{ \begin{verbatim} Name: VXI Device Type register Offset: @0002 read 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Model Code | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Model Code = 0x0100 (256) for the ROCO card \end{verbatim} } \vbox{ \begin{verbatim} Name: VXI Control/Status register Offset: @0004 read/write 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | |Res| write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | |Mod| |Rea|Pas| |Res| read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Control bits (write) : Res : Reset is set by writing a 1 and is cleared by writing 0, or by SYSRESET* Status bits (read) : Res : reflect of Reset bit in control register Pas = 0x1 : Passed set to 1 Rea = 0x1 : Ready set to 1 Mod : Modid* \end{verbatim} } \vbox{ \begin{verbatim} Name: VXI Offset register Offset: @0006 read Unused \end{verbatim} } \vbox{ \begin{verbatim} Name: Serial Number register Offset: @0008 read 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Serial Number | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ \end{verbatim} } \vbox{ \begin{verbatim} Name: Modification Level register Offset: @000A read 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Modification Level | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ \end{verbatim} } \vbox{ \begin{verbatim} Name: Endsubevent register Offset: @000C read/write 31 23 15 07 00 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |err|ROCO number|End Sub Event | | write +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |err|ROCO number|End Sub Event | Word Count |Evt Nbr| read +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ The D16-D31 bits are written from the VME, but the bit D31 is set by a ROCO card if there is a Event Number Fault (ENF). The D00-D15 bits are generated by the ROCO card. \end{verbatim} } \vbox{ \begin{verbatim} Name: Data Fifo Test register Offset: @0010 write 31 23 15 07 00 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | Data Fifo Test | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Writing in this register causes the data to be pushed in the data fifo if the TEST bit of control register is enable. \end{verbatim} } \vbox{ \begin{verbatim} Name: Event Number Test register Offset: @0014 write 31 23 15 07 00 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |Evt Nbr| +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Writing in this register causes the 4 bits data to be pushed in the Event Number fifo if the TEST bit of control register is enable. \end{verbatim} } \vbox{ \begin{verbatim} Name: ROCO Control/Status register Offset: @0016 read/write 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +---+---+---+---+---+---+---+---+---+----+---+---+---+---+---+---+ |ENF|TOR| |DTP| |EDTS|Int|Int|IRF|Tst|Res|Ena| write | | | | | | |TO |ENF| | | |ROC| +---+---+---+---+---+---+---+---+---+----+---+---+---+---+---+---+ |ENF|TOR| |DFF|EFF|FE | | 0 | | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ See the EUROGAM document EDOC077 for more details. \end{verbatim} } \vbox{ \begin{verbatim} Name: Time Outs register Offset: @0018 write 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | Time Out 1 | Time Out 2 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Time Out 1 : 128 micro seconde max, step 8 micro seconde Time Out for the readout (TOR) Time Out 2 : 1 micro seconde max, step 62 nano seconde Time Out for the BLTACK* \end{verbatim} } \vbox{ \begin{verbatim} Name: Interruption/Bus Request register Offset: @001A write 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | |BR Lev | |Int Level | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ BR Level : Bus Request Level from 0 to 3 Int Level : Interrupt Request Level from 0 to 7 \end{verbatim} } \end{document}