This is TeX, C Version 3.14t3 (format=lplain 92.4.6)  5 AUG 1992 18:08
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[] \cmtt/m/n/11 4    On/off Fast Trigger and Validation type       (1=output, 0
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[] \cmtt/m/n/11 5    Output Trigger's TAC word                     (1=output, 0
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[] \cmtt/m/n/11 6    Select Validation line bit 0 (00=not used, 01=Val 1, 10=Va
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[] \cmtt/m/n/11 8    Clear all scalers on the card                         (0=c
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[] \cmtt/m/n/11 9    Program trigger logic LCA           (0 to 1 transition (re
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[]\cmtt/m/n/11 10    Put card in test mode                                 (1=t
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[]\cmtt/m/n/11 12    LCA mode                                             (1=ma
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[]\cmtt/m/n/11 13    LCA reset                                            (1=re
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[]\cmtt/m/n/11 14    Disable LCA                                         (1=dis
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[]\cmtt/m/n/11 15    Readout Mode                         (1=VME LWord reads, 0
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[] \cmtt/m/n/11 0    Level of VXI Clear line                             (1= cl
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[] \cmtt/m/n/11 1    Level of VXI Trigger Sync Pulse line             (1=sync o
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[] \cmtt/m/n/11 2    Level of VXI Go/Stop bit                                  
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[] \cmtt/m/n/11 3    Common Deadtime or Parallel/Pipelined mode. (1=Parallel/Pi
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[] \cmtt/m/n/11 5    Transfer scalers to shadow register              (1= trans
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[] \cmtt/m/n/11 6    Enable Trigger TAC and bypass FT LCA                      
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[] \cmtt/m/n/11 7    Setup Ge TAC                                              
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[] \cmtt/m/n/11 8    Enable External delay                            (1=enable
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[] \cmtt/m/n/11 9    Select Sumbus for CFD setup (bit 0)         (00 = raw Ge, 
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[] \cmtt/m/n/11 10   Select Sumbus for CFD setup (bit 1)         (10 = BGO,    
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[] \cmtt/m/n/11 15   Reset readout and inter-LCA FIFOs [VXIGO must be OFF] (1=r
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[] \cmtt/m/n/11 3        Readout Sequence error  (1=error, 0=OK) (Remains set u
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[24] [25] [26] [27] [28] (latex.aux) ) 
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