Custom Logic registers including MWD in
Lyrtech VHS-ADC cards.
Updated 15/1/09
with new memory map. 18-2-09 added TDRI TS regs 16/3/09 added FIFO status 24/8/09
updates to rev4_x code.
1.
Register Memory Map:
|
Reg add (hex) |
Per card/chan |
Function |
Notes |
|
0-F |
Channel |
MWD control and
status |
2-15 not yet allocated |
|
10-1F |
Channel |
MWD Parameters |
Accesses regs inside MWD code |
|
20-2F |
Channel |
Other per-channel
parameters |
Threshold. 21-2F not yet allocated |
|
30-3F |
Card |
Readout parameters
(common) |
Trace length etc. 31-3F not yet allocated |
|
40-4F |
Channel |
Diagnostics |
Not yet allocated |
|
50-6F |
TBD |
Dead time/ live time
counters and other diagnostics |
Not yet allocated |
|
70-7F |
Card |
Veto and TDRI control |
|
|
80-8F |
Card |
Code version data |
|
|
90-BF |
Card |
Reserved for
diagnostics |
Not yet allocated |
|
C0-FF |
Channel |
Reserved for
diagnostics |
Not yet allocated |
2.
Register Access protocol:
All registers in this
document are accessed via user reg 1 and 2.
To write the registers in this document:
Write to user reg 1
|
31 |
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|
28 |
27 |
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16 |
15 |
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0 |
|
Chan (0-11) |
Register address (0-2047) |
Register value (data) |
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To read the registers in this document, use a 2 stage process:
First write to user reg
2 to define the read address:
|
31 |
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28 |
27 |
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16 |
15 |
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0 |
|
Chan (0-11) |
Register address (0-2047) |
Don’t care (0) |
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Then read user reg 2
|
31 |
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28 |
27 |
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16 |
15 |
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0 |
|
Chan (0-11) |
Register address (0-2047) |
Register value (data) |
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3.
MWD Control and Status registers (0x0 to
0xF)
MWD Control Word (r/w register address 0x0; resets or
powers up to 0x0001, disabled)
0
Disable MWD
(=1) (also resets mwd to reload new parameters when disabled)
1
Disable
Baseline subtraction (=1)
2
Data Shift
0 (lsb) (00 = shift 0; 01 = shift 1; 10
= shift 2; 11= shift 3)
3
Data Shift
1 (msb)
4
Trigger
Polarity (0 for +ve preamp signals, 1 for -ve preamp signals)
5
Test_sel
bit 0 (select the MWD test output data
word 0 = MWDin, 1= DEC2MAUsig,)
6
Test_sel
bit 1 (2= MAU2NORM, 3 = SubOut, 4 =
newALU, 5= newSubOut)
7
Test_sel
bit 2 (6= GetPeak, 7 = trapezsig. Added
for temp diagnostics only)
8
Test_sel
digital_gain bit 0 (00 = x1 read d15-2;
01 = x2 read d14:1;
9
Test_sel
digital_gain bit 1 (10 =x4 read D13:0, 11
= x8 read d12:0 and lsb = 0)
10
GPIO_OE (used for testing
DACs on TDRI)
11
Swap (1 inverts order of DAC data)
12
Use internal trigger (CFD) when =1 or ADAC_TRIG = 0
13
Reset tx_rtdex logic and also latched status bits when 1
14
When =1, put pileup status on MSB of energy (no pileup information
when = 0)
15
When =1 put ADC over-range status on MSB of baseline (no over-range
information when = 0)
MWD Status Word (ro register address 0x1)
Bits 4-8 for ch 1 only
as diagnostic- not reset until reset signal
0
myready
1
mwd_pileup
2
watch_pu
3
decclk_locked
4
watchdog_happened;
5
received_trigger;
6
started_reading_circbuf;
7
finished_reading_circbuf;
8
got_energy
from MWD;
9
mwd_1_active
(not latched)
10
waiting4energy
(trace sent, but waiting for energy)
11
energy_sent
to circ buff
12
reading_flag
(not latched)
MWD Register address 0x2-0xF not used
4.
MWD Parameter Access- register addresses 0x10-0x1F
|
MWD Parameter |
Register Address |
|
0x10 (16) r/w |
|
|
Trapezoid shaping |
0x11 (17) r/w |
|
peak sample |
0x12 (18) r/w |
|
peak separation |
0x13 (19) r/w |
|
baseline average |
0x14 (20) r/w |
|
baseline update
clocks |
0x15 (21) r/w |
|
baseline threshold |
0x16 (22) r/w |
|
decay time |
|
|
decay time (low 16) |
0x17 (23) r/w |
|
decay time (top 8) |
0x18 (24) r/w |
|
decimation |
0x19 (25) r/w |
|
mode |
0x1A (26) r/w |
|
read-only from here down |
|
|
read zero |
0x1B (27) ro |
|
read baseline (low
16) |
0x1C (28) ro |
|
read baseline (top
16) |
0x1D (29) ro |
|
read energy (low 16) |
0x1E (30) ro |
|
read energy (top 16) |
0x1F (31) ro |
In this case the bus
addr lines will be driven from algorithm_register_write_sel(3..0) when
algorithm_register_write_sel(11..4) = 00000001 (binary) and reg_write(n) is
true.
And the bus addr lines
will be driven from algorithm_register_read_sel(3..0) when
algorithm_register_read_sel(11..4) = 00000001 (binary) and reg_read(n) is true.
5.
Other per-channel parameters- register
addresses 0x20-0x2F
CFD Threshold register (r/w register address 0x20)
CFD register default value is 0x0078 (120 dec)
Veto control for each channel (r/w
register address 0x21)
D0 = Apply Veto 1
D1 = Apply Veto 2
D2 = Apply Veto 3
D3 = Apply Veto 4
D4 = Apply Veto 5
D5 = Apply Veto 6
D6 = Apply Veto 7
D7 = Apply Veto 8
D8-D15 not allocated.
(Where more than 1 Veto is applied
the bits are OR’ed together).
ADC Header
register r/w (register address 0x22)
ADC Header
values (defaults embedded in VHDL)
|
Channel |
Header |
Decimal
value |
|
0 |
0EAD |
3757 |
|
1 |
1EAD |
7853 |
|
2 |
2EAD |
11949 |
|
3 |
3EAD |
16045 |
|
4 |
4EAD |
20141 |
|
5 |
5EAD |
24237 |
|
6 |
6EAD |
28333 |
|
7 |
7EAD |
32429 |
|
8 |
8EAD |
36525 |
|
9 |
9EAD |
40621 |
|
10 |
AEAD |
44717 |
|
11 |
BEAD |
48813 |
|
12 |
CEAD |
52909 |
|
13 |
DEAD |
57005 |
|
14 |
EEAD |
61101 |
|
15 |
FEAD |
65197 |
TS control Header register r/w (register address 0x23)
TS
Control Header values (defaults embedded in VHDL)
|
Channel |
Header |
Decimal
value |
|
0 (sync) |
0DAC |
3500 |
|
1 (pause) |
1 DAC |
7596 |
|
2 (resume) |
2 DAC |
11692 |
0x24-0x2F are not yet allocated
Readout parameters (per card)- register
addresses 0x30-0x3F
Trace length register
(r/w register address 0x30)
Trace length register maximum is 1024 (11 bits) (default 0x100)
In rel 4.x this is set to 2 (2 x 32 bit words) and can’t
be programmed)
Pretrigger position register (r/w register address 0x31)
Pretrigger
position register maximum is 2048 (11
bits) (default 0x010)
RTDEX
Read status register (ro register
address 0x32)
Used for all RTDEX reads (channel address
ignored)
D0 = data available (when = 1) (trigger received)
D1= FIFO_available (live status- not latched)
D2 = waiting for rtdex (in loop) (Latched)
D3 = rtdex_start_req (live)
D4 = 1 if dword_cnt_sig = x"00000400" (live status- not latched)
D5 = seq_error
D6 = txenable (live status- not latched)
D7 = rtdex_available (live status- not latched)
D8 = FIFO_event_count_vec(0) (live)
D9 = 0
D10 = ext_trigger received (latched)
D11 = rtdexready1sig (live status)
D12 = FIFO prog_full
D13 = FIFO prog_empty
D14 = FIFO_full
D15 = FIFO_empty
D0-D15
are cleared by control register (0x38) bit D0 going to 1 and enabled when it is
0.
rd_req_fifo live status (read only) (ro register address
0x33)
this is the output of the request fifo (live) (channel address ignored).
FIFO
Write count register (read only) (ro
register address 0x34)
Used for all RTDEX traces (channel address ignored). Status report only.
FIFO
event counter register (read only) (ro
register address 0x35
(event = 512 words) Used for all readout traces (channel address ignored). Status report only.
Ro_enable (status of sequencer)
(read only) (ro register address 0x36)
Used for all channels- bit field says which channel is enable for readout (channel address ignored).
Chan_sel_ro
(status of sequencer) (ro register address 0x37)
Used for all channels- 0-15: says which channel sequencer is reading (channel address ignored).
Read_req (current value from mux)
(ro register address 0x38)
Used for all channels- pattern of read requests from active channels (channel address ignored).
RTDEX
Control register (r/w register address 0x39)
D0 = 1 resets the “data available” bit in RTDEX Read status register (at 0x32 hex)
D0 = 0 allows “data available” to be used again.
D1 = 0 permit hardware reset/rearm of the trigger as soon as it is received
D1 = 1 block hardware reset/rearm of trigger- only runs with software re-arm
D2 = 0 to stop (global disable, set to 0 by MIDAS stop)
D2 = 1 to go (global enable, set to 1 by MIDAS Go)
D3 unused
D4 =1 resets the RTDEX FIFO while set to 1 (direct from register, not from sequencer)
D4 = 0 Idle state- doesn’t reset the RTDEX FIFO.
D5=0 Time Stamp runs normally
D5=1 Clear Timestamp
D6= 0 Use front panel trigger input as external trigger
D6= 1 Use front panel trigger as timestamp synch pulse
D7 = 0 allows- RTDEX_available to be controlled by sequencer (status_rst)
D7 = 1 force RTDEX_Available always on
D8 = 0 allows- FIFO_available to be controlled by sequencer (status_rst)
D8 = 1 force FIFO_Available always on
D9 = 0 normal state- allows buffer FIFO to operate normally.
D9 = 1 is FIFO reset (resets buffer FIFO prior to RTDEX- don’t reset if data available).
D10 = 0 ext trigger uses adac_trig
D10 = 1 ext trigger uses the direct external trigger pulse
D11 = 0 normal
D11 = 1 force reset of adac_trigger while set to 1
D12 = 0 livetime/deadtime counters running
D12 = 1 latch livetime/deadtime counters
D13 = 0 normal operation- (use ext trigger always as either trigger or synch according to D6)
D13 = 1 Use 1st ext trigger or sync after global enable to load timestamp counters from 0x3A-3C
(This bit over-rides the settings of D6 in this register(ext
trigger/synch selection) and of MWD control word bit 12, reg offset 0,
(internal/external trigger selection).)
D14 = 0 If D13 = 1 then add a 5ms delay onto global enable before looking for trigger to load TS
D14 = 1 Disable 5ms delay and (if D13 = 1) look for trigger straight after global enable to load TS
D15 unused
Timestamp Low Preload Value (default 0x001A) (rw register address 0x3A)
Used for all channels- low word of timestamp (15..0)- loaded every synch or at resynch
Timestamp Mid Preload Value (default 0x0000) (rw register address 0x3B)
Used for all channels- middle word of timestamp (31..16)- loaded at resynch only
Timestamp High Preload Value (default 0x0000) (rw register address 0x3C)
Used for all channels- top word of timestamp (48..32)- loaded at resynch only
Timestamp
logic latency correction (default 2) (r/w register, 4 bits wide, address 0x3D)
Used for all channels- added to TS Low Preload value to correct for sequencer pipelining in steps of 1 clock from 0-15 (4 bits only).
FIFO_Status
register (r/o register 16 bits wide, address 0x3E)
D0-D6 = req_rtdex_count
D7-11 not used
D12 = FIFO prog_full
D13 = FIFO prog_empty
D14 = FIFO_full
D15 = FIFO_empty
Register 0x3F- not yet allocated
6.
Diagnostics - register addresses
0x40-0x4F
Registers 0x40-0x4F re- allocated (Header moved to 0x22)
0x40 (read only) Next Cycle counter
0x41 (read only) ext trig rst req counter
0x42 (read only) rf_rd_en counter
0x43 (read only) rf_wr_en counter
0x44 (read only) valid_rd_req counter
0x45 (read only) rf_valid counter
0x46 (read only) Status bits for readout sequencers (live)
|
0 |
Readout active |
|
1 |
Ro seq busy |
|
2 |
reading |
|
3 |
Ext trig rst req |
|
4 |
Next cycle |
|
5 |
Chan sel ro5(0) |
|
6 |
Chan sel ro5(1) |
|
7 |
Chan sel ro5(2) |
|
8 |
Chan sel ro5(3) |
|
9 |
Chan sel ro5(4) |
|
10 |
Valid read req |
|
11 |
mwd_active_sig |
|
12 |
rf_empty |
|
13 |
rf_full |
|
14 |
rf_prog_empty |
|
15 |
rf_prog_full |
0x47 (read only) Status bits for pause and resume (live)
|
0 |
Pause Tag |
|
1 |
Resume Tag |
|
2 |
Rd Req Fifo(16) |
|
3 |
Pause |
Top 8 bits used for sequencer state number: D15:12 = rcbstate; D11:8 = cspstate.
0x48 (read only) Trace Done counter
0x49 (read only) Mwd Finished counter
0x4A (read only) Readout Active counter
0x4B (read only) Readout Seq Busy counter
0x4C (read only) Clock_TS_Active counter
0x4D (read only) Resume Request counter
0x4E (read only) Pause Request counter
7.
Livetime registers 0x50 to 0x5f (from rel 1.c
onwards)
0x50 rtdx_LT_count(15:0) (r/o)
0x51 rtdx_LT_count(31:16) (r/o)
0x52 rtdx_DT_count(15:0) (r/o)
0x53 rtdx_DT_count(31:16) (r/o)
0x54 fifo_LT_count(15:0) (r/o)
0x55 fifo_LT_count(31:16) (r/o)
0x56 fifo_DT_count(15:0) (r/o)
0x57 fifo_DT_count(31:16) (r/o)
0x58 test register (r/w)
8.
Diagnostics register addresses 0x60-0x6F
0x60 (read only) clockts(0) counter
0x61 (read only) clockts(1) counter
0x62 (read only) clockts(2) counter
0x63 (read only) clockts(3) counter
0x64 (read only) clockts(16) counter (synch)
0x65 (read only) last length count (write to pre-rtdex fifo)
0x66 (read only) length count status
D15:12 = error count
D11:3 = low 9 bits of length count
D2 = length < tracelength
D1 = length > tracelength
D0 = length = tracelength (normally =1)
9.
TDRI and Veto control registers (common)
0x70-0x7F
TDRI Control register 0x70 (r/w register, 16 bits wide)
D0 = DAC output signals
enable (0 = off, 1 = enabled)
D1 = DAC Channel select
bit 0
D2 = DAC Channel select
bit 1
D3 = DAC Channel select
bit 2
D4 = DAC Channel select
bit 3
D5-15 not yet allocated
Veto Coincidence Window Register 0x71 (r/w register, 16 bits wide)
Number of 10ns steps used for Veto Coincidence
window (either counts from Veto and looks for trigger or counts from trigger
and looks for Veto depending which comes first).
e.g. 0x80 = 128x 10 ns = 1.28us window.
10.
Code version data (per card)- register
addresses 0x80-0x8F
All
code version registers are read only
Code
Major Release Version number (major changes) register (ro register address
0x80)
Hex values 0x0000 to 0xFFFF are valid
Code
Incremental Release number (update for
every change) (ro register address 0x81)
Hex values 0x0000 to 0xFFFF are valid
Number of channels supported in
this version (ro register address 0x82)
Bits 0-7 Decimal value from 1-16 (hex value 0x0001 to 0x0010)
Bits 11-8 set to 0x0 for normal readout; 0xF for rel 4.x min event
length mode (header, 28 bits TS, energy
and 4 flags only, no trace and no option to increase tracelength above 2).
Bits 15-12 set to 4 (4 bytes) for 32 bit wide operation (earlier 16 bit versions were set to 0 or 2).
Date
of this version (ro register address 0x83)
Hex version of date (day/day/month/year) so 21st July 2009 is coded as 1579
11.
Data
format for Lyrtech readout
|
D31 to D16 |
D15 to D0 |
|
|
TS_low (15:0) |
Header |
|
|
Flags (d28=Veto; d29=pileup, d30=adc ovr, d31= spare flag ) |
TS_mid (27:16) |
energy |
Notes
on data signed/unsigned.
ADC data into Custom code are 14 bits. D15 is connected to overflow and D14 copies D3 (sign).
All 16 bits go into the trace and raw data. However, only 14 bits (d13:0) are used for MWD, and CFD code.
Signed to Unsigned code at start of MWD interprets the 14 ADC data bits D13:0 like this:
NB Positive and negative refer to data at the ADC which is same polarity as the front panel input in Lyrtech VHS-ADC (GRT4 inverts data between input and ADC).
|
|
ADC data from ADC |
If “positive” at ADC (pol = 0) |
If “negative” at ADC (pol = 1) |
|
+ve FS |
01 1111 1111 1111 |
0x3FFF |
0x0000 |
|
0 |
00 0000 0000 0000 |
0x2000 |
0x1FFF |
|
0 |
11 1111 1111 1111 |
0x1FFF |
0x2000 |
|
-ve FS |
10 0000 0000 0000 |
0x0000 |
0x3FFF |
So now there is no sign bit, but the data increase in the direction of the signal’s increase.
Bipolar signals are handled correctly because 0v is coded as 0x2000 in both cases.
Processing of data:
· Signed2unsigned produces 14 bits unsigned values 0 to 0x3FFF.
(Input is ADC(13:0); Output is unsignedout(13:0) which feeds
MWDin of mwdinstanz module which starts with decimation.)
· Decimation: increases 14 to 18 bits, no possible sign change: unsigned values 0 to 0xFFFC.
(Input port called MWDin(13:0) receives MWDin(13:0) signal.
Output port is DEC2MAUsig(17:0). Decimation factor is 4 (was 16 at times in the
past, hence 18 bits out when only 16 are needed or used.).
· Moving window deconvolution- Use MAU to output delayed and mirrored copies of the DEC2MAU(15:0) signal. Subtract delayed value from current value and save both the difference and the carry bit. Within the MAU, accumulate the differences to make a 24 bit value, MAU2NORMsig(23:0) signal which represents the are under the pulse. While the differences may be negative due to noise or on the tail of the pulse, the accumulated value (area) should always be positive because the input is always positive as a result of the signed2unsigned unit. Maximum for MAU2NORM is 256 x 0xFFFC = 0xFFFC00. Subout can be + or – 65535 (0xFFFF).
MAU input port receives DEC2MAU(15:0) and shape_time
controls difference and size of accumulated result. Output is called
MAU2NORMSIG(23:0). The external subtraction unit takes 16 bits signals mau_inst
and mau_del from MAU. After subtraction the difference is output as
subout(15:0) with the carry (sign) bit in subout(16). To match the 24 bits of
the multiplication, the subout signal becomes newsubout(23:0) where lowest 7
bits are 0.
· Multiplication to correct for decay time constant. The accumulator output is scaled by a multiplication factor derived from the decay time constant, the shaping time and the clock. The ALU output is 24.24 bits but in fact can only be 16.24 because of the normalisation (decaytime includes area/length term) so we ignore the 8 MSBs (always 0) and include 8 of the 24 fractional bits making a 16.8 number made up from bits 39 down to 17 of the multiplier output (23 bits) with the 24th bit being forced to 0 because we need a signed value to add to the signed difference in the last part of the MWD.
Inputs are MAU2NORMSIG(23:0) and decaytime(23:0) resulting
in ALUout(47:0) which becomes NewALU(23:0) with NewALU(23) = 0 and NewALU(22:0)
= ALUout(39:17).
· Final part of deconvolution- addition of signed difference and unsigned corrected area resulting in a square pulse with a flat top (if the shaping time correction is done right).
Inputs are newsubout(23:0) and NewALU(23:0) with outputs
MWDSIG(24:0) where MWDSIG(24) is the carry out (sign) bit and MWDSIG(23:0) is
the value.
Comment in the code:
-- carry out will be
ignored, is equal to MWDsig(TwentyFourBits-1)
· Trapezoidal filter- accumulation based action- no sign change.