Silena 9418 32 channel ADC module

Specification:

SlLENA Mod. 9418/6-V VME 6U
32 CHANNELS PEAK SENSING 12 BIT (4096 channel) ADC
(V430 Standard)

Hardware:

6U VME Format
VME interface is A32/D16
Address space required is 64 Kbytes
VME Base Address is selected using the jumpers S2 and S3. A jumper installed is seen as a logic 0.
For use with MIDAS the base address should always be less than 0x06000000.
The photograph shows a module with the VME base address set to 0x02000000.

You can obtain a full size high resolution version of the photograph here.

Operating mode selection (J1):

For VME operation jumper J1 should be OPEN

/GATE source selection (J14):

The behaviour of the /GATE signal is like that of an INHIBIT signal. Triggers (COM input) are not accepted when the /GATE signal is present. In the VME operating mode J14 pins 1-2 should be CLOSED in order that the /GATE input is taken from the front panel.

J15:

The header J15 is for internal purposes. It should always be configured with pins 2-3 CLOSED.

GLINH-GLTRG (JP1 & JP2):

In the VME operating mode when only one module (i.e. only one ADC) is present it is possible to enable the ADC module to internally generate the GLTRG signal at the GLINH occurrence. This occurs when both JP1 and JP2 headers are CLOSED.
When more than one front end module is present in the system and the acquisition is performed in multievent mode, this “auto-GLTRG” option may cause a loss of event syncrhonization among the modules. In this case the JP1 and JP2 headers should to be left OPEN. The management of all signals (MDTRG, GLINH, GLTRG, RJTRG) has to be performed by external electronics. The Silena Acquisition Control (SAC) card has been developed for this purpose.
Note - MIDAS uses the SAC in such a way that while it is preferred that JP1 and JP2 are OPEN so that the SAC controls the GLTRG signal in most cases the hardware will operate correctly even with JP1 and JP2 CLOSED.

Front panel signal termination (T1 & T2):

In the normal configuration the SAC module controls one or more ADC modules by means of the signals (GLINH, GLTRG, etc.) present on the front panel connector by means of a single flat cable. In this case it is necessary to remove the resistive array terminators T1 and T2 of all the modules but the last one.

Note - The value of T1 is 47 Ohms and T2 is 2.2 KOhms.

Acquisition control signals:

The following acquisition control signals are present on the front panel command bus.

signal

direction

ECL type

description

COM

input

differential

module input trigger

MDTRG

output

single ended

module trigger acknnowledgment

/GATE

input

differential

trigger acknowledgment inhibit

RJTRG

input

differential

reject current trigger

GLTRG

input

differential

acknowledgment (validation) of the trigger ocurrence

GLINH

output

single ended

module busy

Operational Notes

1) Silena 9418/6V ADC COM signal should precede the peak of the analogue input by >500ns for semi-gaussian (or similar) shaping.

2) Silena 9418/6V ADC COM signal should follow the rising edge and precede trailing edge for a `flat top' signal (for example, from a linear gate & stretcher). Nominal linearity requires the width of the analogue input signal during the measurement interval ( COM + RTP ) to be 1us, or more.

Example of command bus connections:

Example time diagram of the control signals:

We suppose that we have 2 ADC modules A and B. Only the module A receives the trigger.

1. Module A receives a trigger (COM) input
2. Module A generates a MDTRG signal to inform the external electronics (SAC) of the trigger occurrence
3. Module A asserts a GLINH signal to inform the SAC that it is performing the elaboration of the event (conversion of input signal)
4. The SAC, after a "trigger window" internal delay, asserts a GLTRG signal to all the ADCs to inform the system that a valid trigger has occurred.
5. All the ADCs have permission to store the event in their own internal data FIFOs. Module A will store the data converted and module B will store only the END OF EVENT word to keep a record of the event. The GLTRG signal will inhibit all ADCs from accepting another trigger.
6. The GLTRG signal is kept asserted while any ADC module asserts the GLINH signal. When all ADCs have deasserted GLINH then the SAC deasserts the GLTRG signal.
7. The system is ready to accept the next trigger.

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