R3B ASIC User Manual v 3.0.3
(For R3B ASIC v3)
Changes from 3.0 |
Misaligned “Pad Type” entries from pins 66-87 in section 19 “Pin list” |
Changes from 3.0.1 |
Chapter 17, Calibration capacitor changed from 1.1pF to 2.9pF |
Changes from 3.0.2 |
Chapter 16.5., Added registers new to ASIC V3 (4 bits of 0 and 8&9) |
Lawrence Jones
Last Modified:
Wednesday, 06 May 2015 : 4:13 PM
R3B ASIC User Manual
R3B (Reaction studies with Relativistic Radioactive Beams) is a fixed-target detector system with high efficiency, acceptance, and resolution for kinematically complete measurements of reactions with high-energy radioactive beams. It will be located at the focal plane of the high-energy branch of the Super-FRS (Fragment Separator), which is a magnetic spectrometer. This experiment forms part of NUSTAR (Nuclear Structure Astrophysics and Reactions) and will be installed at FAIR (Facility for Antiproton and Ion Research) in Germany.
Detectors will track and identify a radioactive beam onto and out from a reaction target, Light charged particles and gamma rays from the target region will be measured by the target recoil detector. This detector surrounds the target volume and consists of two main elements: the Si tracker and the calorimeter. The Si tracker is a three-layer silicon micro-vertex tracker, providing precise tracking and vertex determination as well as energy and multiplicity measurement.
The R3B ASIC is intended for reading out, processing and digitising signals generated by ionising particles passing through the silicon strip detector. These signals are comprised of either electrons or holes depending on the polarity of the detector.
A block diagram of the ASIC is shown in figure 1.
Figure 1: Block Diagram of the R3B ASIC
Each channel of the ASIC consists of a charge sensitive Preamplifier, Shaper, Peak Hold, Gain Amplifiers, Comparators and Control Logic. The remaining chip functionality consists of an Analogue Miultiplexer, ADC, Data Buffer, 128 bit OR, Timestamp Counter, Control Logic and I2C Interface and Registers.
The preamplifiers remove most of any signal charge from any detector strips which are hit by ionising particles. These charges are integrated onto the feedback capacitors of the preamplifiers into a voltage signal proportional to the energy of the ionising particles which generated the charge. These voltages are then filtered by the CR-RC shapers to reduce noise and generate output pulses which feed into th peak hold circuits where the signal amplitudes are saved prior to digitisation with a 12 bit successive approximation register ADC
There are two comparators in each channel, one connected to an amplified version of the preamplifier output, and the other connected to an amplified version of the shaper output. The former is used to generate a timestamp and the latter used to generate minimum energy threshold below which no signals are read out. Any signal above the energy threshold is a "hit" and this also triggers the readout of any neighbouring channels. An analogue multiplexer outputs the voltage from each hit channel to the ADC where it is converted to 12 bits. Each channel is dynamically reset once the signal has been saved.
Channel control logic sequences the resets, determines which channels require reading out and latches the timestamp. Digital data output from each hit channel includes the 15 bit timestamp and 7 bit channel address. An additional bit indicates whether the timestamp is valid.
Multiple chips are daisy-chained together with one chip acting as a master and the others as slaves. The master chips detects whether data is available to be read out and then each hit chip outputs a set number of data frames before passing the token on to the next chip. A 32 deep data buffer holds the channel data for each hit until it can be read off chip. Control logic sequences the readout and controls the daisy chaining.
An additional output from the ASIC is a 128 bit OR of all the hit channels which can be used as a trigger.
A diagram of the preamplifier operating in Electrons mode is shown in figure 2. The preamplifier is comprised of a differential amplifier with one input biased to a programmable voltage and the other input connected to one strip of the detector. A capacitor connects in negative feedback between the output of the preamplifier and the input connected to the detector. Thus any charge generated on the detector strip is removed by the preamplifier and integrated on the feedback capacitor. The voltage generated at the output of the preamplifier is proportional to the charge. The dynamic range of the preamplifier is 50MeV. The lowest energy that will be measured is about 40keV so the noise level of the full channel including the preamplifier should be about 8keV.
The preamplifier is DC connected to the detector strip, so any leakage current present in the detector will get integrated on the feedback capacitor and will push the preamplifier into saturation. A leakage compensation circuit is connected in negative feedback across the preamplifier and provides a path to source or sink the detector leakage current so that it does not get integrated on the feedback capacitor. The voltage bias to the compensation circuit is trimmable to eliminate effects of transistor mismatch. This is necessary since the offset of the preamplifier will be different when the reset is active. The specification for the leakage compensation circuit is for currents up to 100nA in both polarities but it should typically be not more than 20nA at nominal operating temperatures (40C).
In the case of a low bias current to the leakage compensation circuit it may not provide sufficient DC stability to the preamplifier. For this reason an additional feedback circuit is included which has a constant current biased transistor in the feedback.
Figure 2: Preamplifier
Configured for Electrons Mode
An additional circuit limits the response of the circuit to very large signals to aid recovery following overload conditions. There is also a circuit which is used to reset the preamplifier.
The preamplifier also has programmable compensation capacitors to optimise the rise time for the detector strip capacitance.
Figure 3 shows the response of the preamplifier to a signal when in electrons mode. The signal is positive going so the preamplifier must be biased at about 0.7V to give maximum dynamic range. The rise time of the preamplifier will be determined by the detector capacitance and the Miller compensation setting. If there were no channel reset, the preamplifier would take several 100 microseconds to recover for large signals. However, there is a reset and the delay before the reset is programmable. Worst case data rates should be 5kHz/channel with an occupancy of 15%.
Figure 3: Electron
mode transient response.
The Miller compensation should be set to minimise the rise time while keeping the amplifier stable. This will depend on the input capacitance and therefore the detector strip length. The capacitance can vary from a few pF up to 80pF.
Figure 4: Holes mode
transient response.
The response of the preamplifier to signals in holes mode is shown in figure 4. In this case, the signal is negative going so the preamp should be biased at about 2.3V. The dynamic range of the preamplifier is the same in both holes and electrons modes.
On occasion there may be large signals in the region of 1GeV and the circuit needs to able to recover from this. The channel reset goes some way to doing this however there is an overload recovery circuitt which automatically protects the preamplifier against large signals.
A summary of the specification is shown below:
·
Signal
polarity –
either electrons or holes.
(programmable)
·
Coupling to detectors – DC.
·
Detector leakage current – 0-100nA, typically 20nA,
both polarities. Automatically controlled.
·
Detector capacitance
– variable, from few pF up to ~ 80pF.
·
Overload recovery – within 10us for 1GeV signal.
·
Data rate – Dependent on position in detector. Worst
case: 5kHz/channel
·
Occupancy – Dependent on position in detector. Worst
case: 15%
·
Energy range – 0-50MeV.
·
Lowest energy to be measured – 40keV.
·
Resolution and noise threshold – 8keV RMS (19keV
FWHM).
Figure 5: Programmable
CR-RC Shaper
The shaper (figure 5) is comprised of a differential amplifier, a resistor and capacitor network in series with the input, and a resistor and capacitor network in feedback across the amplifier, all forming a CR-RC shaping configuration. The amplifier is biased up with a programmable voltage and the shaping time is selectable between 0.5us and 8us using the programmable capacitor arrays. As with the preamplifier, the shaper is configurable for reading both electrons and holes (by changing the bias voltage VSHA) and there is a circuit for resetting the shaper.
Figure 6 shows the shaper response to a signal while in electrons mode. The signal is negative going so the shaper needs to be biased at about 2.4V. For Holes the signal would be positive going so the shaper should be biased at 0.6V.
Figure 6: Shaper
Electrons Mode Transient Response
The bottom trace shows the response with a channel reset occurring while the signal is still active. The response to holes is shown in figure 7.
Figure 7: Shaper Holes
Mode Transient Response
A summary of the specification is shown below:
·
Signal
polarity –
either electrons or holes.
·
Peaking time programmable 500ns-8us, 4 bits.
The 10x Gain amplifier (figure 8) uses a differential amplifier together with capacitive gain to amplify the signals from the preamplifier and shaper prior to applying these to the comparators. This is necessary since the required minimum signal required at the output of the shaper would be of the order of 2mV, which is insufficient to set a comparator threshold. There is a feedback circuit which provides DC stability and a circuit which is used to reset the amplifier. The circuit is configurable for holes or electrons. In both modes the amplifier is biased at 1.5V.
Figure 8: 10x Gain
Amplifier.
The 10x Gain Amplifiers form the input to the comparators. The amplifiers and comparators will have some offset associated with them which will vary from channel to channel. In order to cancel this out, the differential amplifiers have a programmable offset which is used to trim the input to the comparators. This can be trimmed in a positive or negative direction over a few hundred mV to 7 bits resolution.
There are two identical comparators used within each channel. The first one is connected to the 10x Gain Amp connected to the preamplifier and a programmable threshold voltage is used to generate a timestamp from the fast leading edge of the preamplifier output. The second comparator is connected to the 10x gain amplifier connected to the shaper and a second programmable threshold voltage is used to define the signal energy level at which a "hit is generated. Only signals above this level are read out. Although there is no circuit to specifically reset the comparator, the outputs from the comparators are latched within the channel control logic and these latches require resetting. A polarity switch determines whether it is working in holes or electrons mode.
The peak hold circuit connects to the output of the shaper where it follows the signal on its output before holding the peak of the voltage. The circuit contains two amplifiers, one is used when reading holes the other used when reading electrons. The amplifier not used in the peak hold configuration is used as a sample and hold buffer. An additional circuit provides a small trickle current which biases the peak hold circuit up as a slow buffer. When the energy threshold comparator fires, this trickle current is switched off and the circuit switches to peak hold configuration. The small trickle current means that the peak hold circuit does not require periodic resetting, but only requires resetting once the channel has been read out.
Figure 9: Peak Hold
in Holes Configuration
Figure 9 shows the peak hold circuit in holes mode. The signal Rst initialises the circuit by discharging the capacitor CPH. With SampleB on and Sample off, the voltage VPH follows the signal from the shaper. A small trickle current is present while the signal remains below the energy threshold (controlled by HitB). This ensures that when there are no signals present for a long time the peak hold circuit does not drift. Once the signal is above threshold the trickle current switches off and the circuit acts as a standard peak hold. A predetermined time after the voltage has peaked, the Sample signal switches on (and SampleB off) to sample the voltage on CSH where it is buffered by the second amplifier on to the analogue multiplexer. Figure 10 shows a the signals operating in a typical readout cycle.
Figure 10: Peak Hold
Operation
The analogue mutliplexer is comprised of 128 complementary switches connecting the output of each peak hold to a common node. It is controlled by the channel readout logic.
The digital multiplexer is comprised of tristate buffers. It connects the 7 channel addresses,15 timestamps bits and the "hit" bit from each channel onto common bus nodes.
The Channel Readout Logic has 4 main functions:
Firstly, it detects when a channel has been hit and sequences the sampling of the data at the output of the peak hold circuit. This has to be done once the Shaper has peaked, and to ensure this the sampling time is programmable.
The second function of the logic is to control the resetting of the channels once the data has been sampled. The Preamp, Shaper and 10xGain amps have a fixed reset length, however, the length of time that the peak hold reset is held on is programmable using a 4 bit register.
The third function is to read out the data from channels which have been hit. The latched hit signals from all channels are ORed together to determine whether there is any data to read out. If there is, a shift register is initialised, which shifts down from channel 0 to channel 127, stopping in those channels with data to read out, and skipping those channel which have nothing. It returns to its waiting state if there is nothing else to read out or repeatedly cycles around the channels until there is nothing left. The rate at which it does this is 1MHz. Data output from the channel include the timestamp and channel address. The analogue output from the channel is passed to a multiplexer.
The last function of the channel readout logic is to generate a "trigger signal" which can be transmitted off chip. A pulse is generated within each channel when the preamplifier comparator fires.. The leading edge of the pulse is synchronous to the comparator signal, whilst the trailing edge is synchronised to the clock. The length of this pulse is programmable using a 4 bit register. An 128 bit OR of all these trigger pulses is transmitted off chip.
Figure 11: Channel
Readout Logic Timing
Figure 11 shows the timing of the channel readout logic. A hit occurs asynchronously in a particular channel at time (0). On the next rising edge of the clock (1) the hit is detected by the state machine and it begins sequencing the readout into the sample and hold circuit. Depending on the particular shaping time the data must be sampled after the shaper output has peaked, with the peak being held on the peak hold circuit. The time at which sampling starts (2) is therefore programmable with minimum separation from (1) being 2 clock cycles.
Once the channel has been sampled it can be reset. All resets come on simultaneously, but are sequenced to switch off as follows. Preamplifier after 2 clock cycles, Shaper after 3 clock cycles, Peak Hold and channel logic after 4 clock cycles plus a programmable number of clock cycles.
The ASIC has one 12 bit successive approximation ADC. The ADC continuously runs at a rate of 1M Sample/s. When its output contains hit data it is written into the data buffer to await readout. The ADC also has a test mode where the input sample and hold buffer can be bypassed and a signal applied directly into the ADC from an addition bondpad. This function is controlled by a bit in a control register.
The data buffer is a 48bit wide 32 deep FIFO. It stores the following data per hit while they are waiting to be read out:
·
7 bit channel address
·
15 bit timestamp
·
1 bit hit
·
12 bit ADC data
Once
the buffer is full, no more data can be written into it until something has
been read out. A count is kept of the number of data packets that have been
blocked. This count can be read and reset by I2C commands to REG7.
The chip control logic performms several functions.
The ASIC can run off a 100MHz or a 200MHz input clock whilst, the data is read off at a rate of 50Mbits/s and the ADC runs at 1Msample/s. The clock block generates the 50Mhz clock from the 100MHz or 200MHz input clock. A prgorammable register bit defines whether the input clock being used is either 100MHz or 200MHz. The 1MHz clock is generated from the 50MHz clock. For the case of daisy chained chips, another control bit determines whether the internally generated 50MHz clock is used (master chip) or whether it accepts an externally generated 50MHz clock (slave chip).
The VAL input has 3 functions. which are determined by setting the relevent bits in a control register.
The input can used as a Validate control to reduce the amount of data read out of the chip. The input is used to make a hit valid for readout. The VAL input must be high at the point where the data is saved in a channel for it to be written into the data buffer. If the input is low when this occurs then no data will be written into the data buffer and therefore no data will be read off chip for that particular hit. The channel will continue to process the data, and reset itself as usual, it is just not stored in the data buffer to be read out. In a second mode it can be set permanently high.
The input can be used as Calibrate control. A pulse applied on this input will generate an analogue calibrate pulse to any channel selected for calibration.
The input can be used to reset the timestamp counter, thus synchronising the timestamps of all chips it is applied to.
VM1 |
VM0 |
Function |
0 |
0 |
Validate – VAL input used to
validate a hit |
0 |
1 |
Calibrate – VAL input used as pulse
for calibration |
1 |
0 |
Time Stamp Reset – VAL input
resets the Counter |
1 |
1 |
VAL input not active – Validate
permanently on |
This circuit generates timing signals for the data register and the ADC.
The daisy chain control sequences the readout of data off chip and from chip to chip. Four chips are connected in the chain (figure12 and 13).The first chip acts as master and generates the 50MHz clock which is used to transmit the data. The master also initialises the readout by looking for data valid signals (DAV) being passed down the chain. The master transmits its own data and the 50MHz readout clock to the next in the chain, which then passes these on and so on to the last chip in the chain. When a chip has finished transmitting it passes a read enable token to the next chip in the chain. The REN signals from each chip remain active until the last in the chain has read out and passes its REN to the master. The master then releases its REN signal and this propagates along the chain. The last chip in the chain can output data Manchester Encoded. The number of data packets output by each chip before passing to the next is programmable up to 256.
Figure 12: Daisy-chained ASICs
Figure 13: Daisy Readout Sequence
A data register is loaded with data packets from the data buffer and then shifts them off chip. It also accepts the data being transmitted from a previous chip in the chain. Figure 13 shows the order of the data packet which is transmitted off chip. A data packet is comprised of the following: 2 start bits (11) 10 bit chip address, 7 bit channel address, 15 bit timestamp, 12 bit ADC data, 1bit hit bit, 1 stop bit (0).
Figure 14: Data Packet
There is selectable Manchester Encoding on the data output. For the avoidance of doubt, Manchester encoding means that transitions happen in the middle of the clock edge only and a 0 is represented by a 0-1 transition and a 1 by a 1-0 transition (figure 15).
Figure 15: Manchester
Encoded Data
On-chip control registers are accessed through an I2C interface. The interface on the ASIC is purely a slave device and is written to and read from in the following I2C format:
I2C Start : 7 bit Chip Address : 0 : Ack : 8 bit Register
Address : Ack : 8 bit Data : Ack : I2C
Stop
I2C Start : Chip Address : 0 : Ack : Register Address : Ack :
Stop : Start : Chip Address : 1 : Ack : Read Data : Ack : I2C Stop
The interface will acknowledge I2C transactions at the correct points in the procedure.
Since there are more than 256 register on each chip it is necessary to use paging to access these. There are 128 pageless registers and 4 pages of other registers. The pageless registers are those register with addresses 0-127. All paged registers have addresses 128-255 and have to be accessed by first defining the page on which they are located. This is done by loading the register with address 0 with an active high bit in one of four locations. Bit location 0 corresponds to page 0, bit location 1 corresponds to page 1, bit location 2 corresponds to page 2 and bit location 3 corresponds to page 3.
The I2C interface accepts addresses from 16 upwards only. This is a change from the previous version of the chip.
The function of each register and its page number are listed in
the following tables:
The following registers have addresses 0-5 and control the operation of the ASIC. These registers are both writable and readable via I2C:
REG0 |
Function |
Default |
Description |
7 |
Lvds_Dis4 |
0 |
1disables bottom edge neighbour |
6 |
Lvds_Dis3 |
0 |
1 disables top edge neighbour I/O |
5 |
Lvds_Dis21 |
0 |
1 disables Last daisy LVDS |
4 |
Lvds_Dis1 |
0 |
1 disables Master daisy LVDS |
3 |
Page3 |
0 |
1 to write/read page 3 |
2 |
Page2 |
0 |
1 to write/read page 2 |
1 |
Page1 |
0 |
1 to write/read page 1 |
0 |
Page0 |
0 |
1 to write/read page 0 |
REG1 |
Function |
Default |
Description |
7 |
Electrons |
1 |
1=Electrons, 0=holes |
6 |
NNEN |
1 |
Enable Neighbours |
5 |
VM1 |
1 |
Validate Mode bit 1 |
4 |
VM0 |
1 |
Validate Mode bit 0 |
3 |
N/C |
- |
|
2 |
N/C |
- |
|
1 |
N/C |
- |
|
0 |
N/C |
- |
|
REG2 |
Function |
Default |
Description |
7 |
TrigSel |
0 |
1=Select Shaper as Trigger |
6 |
FirstChip |
1 |
1=Sets Chip as 1st in
Chain |
5 |
LastChip |
0 |
1=Sets Chip as last in Chain |
4 |
SelIntClk |
1 |
1=Uses Internal 50MHz Clock |
3 |
Sel100 |
0 |
0=200MHz, 1=100MHz |
2 |
EnTS |
1 |
1=Enable Time Stamp |
1 |
EnTest |
0 |
1=Enable ADC Test In |
0 |
EdgePads |
0 |
1= Enable Top/Bot Pad |
REG3 |
Function |
Default |
Description |
7 |
RstDel3 |
0 |
Reset Off Delay bit 3 |
6 |
RstDel2 |
0 |
Reset Off Delay bit 2 |
5 |
RstDel1 |
0 |
Reset Off Delay bit 1 |
4 |
RstDel0 |
0 |
Reset Off Delay bit 0 |
3 |
TrigDel3 |
0 |
Trigger Length bit 3 |
2 |
TrigDel2 |
0 |
Trigger Length bit 2 |
1 |
TrigDel1 |
0 |
Trigger Length bit 1 |
0 |
TrigDel0 |
1 |
Trigger Length bit 0 |
REG4 |
Function |
Default |
Description |
7 |
Tshap3 |
0 |
Shaping Time 3 (to peak) |
6 |
Tshap2 |
0 |
Shaping Time 2 |
5 |
Tshap1 |
1 |
Shaping Time 1 |
4 |
Tshap0 |
1 |
Shaping Time 0 |
3 |
SDel3 |
0 |
Delay after Peak bit 3 |
2 |
SDel2 |
0 |
Delay after Peak bit 2 |
1 |
SDel1 |
1 |
Delay after Peak bit 1 |
0 |
SDel0 |
0 |
Delay after Peak bit 0 |
REG5 |
Function |
Default |
Description |
7 |
NPD7 |
1 |
Number of Data Packets bit 7 |
6 |
NPD6 |
0 |
Number of Data Packets bit 6 |
5 |
NPD5 |
0 |
Number of Data Packets bit 5 |
4 |
NPD4 |
0 |
Number of Data Packets bit 4 |
3 |
NPD3 |
0 |
Number of Data Packets bit 3 |
2 |
NPD2 |
0 |
Number of Data Packets bit 2 |
1 |
NPD1 |
0 |
Number of Data Packets bit 1 |
0 |
NPD0 |
0 |
Number of Data Packets bit 0 |
The following registers 6-7 are only readable via the I2C. Bits
7 and 6 of REG6 contain the full and empty flags of the readout buffer. Bits
5-0 contain the PCB address. REG7 contains the count for the number of blocked
data when the buffer is full.
REG6 |
Function |
Default |
Description |
7 |
Empty |
- |
Buffer Empty Flag |
6 |
Full |
- |
Buffer Full Flag |
5 |
PCBAdd5 |
- |
PCB address bit 5 |
4 |
PCBAdd4 |
- |
PCB address bit 4 |
3 |
PCBAdd3 |
- |
PCB address bit 3 |
2 |
PCBAdd2 |
- |
PCB address bit 2 |
1 |
PCBAdd1 |
- |
PCB address bit 1 |
0 |
PCBAdd0 |
- |
PCB address bit 0 |
REG7 |
Function |
Default |
Description |
7 |
BLCKD7 |
- |
Blocked Data Count bit 7 (prevents
further counts above 128) |
6 |
BLCKD6 |
- |
Blocked Data Count bit 6 |
5 |
BLCKD 5 |
- |
Blocked Data Count bit 5 |
4 |
BLCKD 4 |
- |
Blocked Data Count bit 4 |
3 |
BLCKD 3 |
- |
Blocked Data Count bit 3 |
2 |
BLCKD2 |
- |
Blocked Data Count bit 2 |
1 |
BLCKD 1 |
- |
Blocked Data Count bit 1 |
0 |
BLCKD0 |
- |
Blocked Data Count bit 0 |
Addressing register 7with a write command does not write
anything into the register but is used as a means of resetting the blocked data
count:
REG7 |
Function |
Default |
Description |
I2C write |
RSTCNT |
- |
Resets the Blocked Data Count |
The following registers are new to the ASIC V3:
REG8 |
Function |
Default |
Description |
7 |
RENval |
0 |
REN override value |
6 |
OrREN |
0 |
Overrides RENout |
5 |
DAVval |
0 |
DAV override value. |
4 |
OrDAV |
0 |
Over rides DAVout |
3 |
RENinMon |
- |
Readonly. Monitors RENin |
2 |
DAVinMon |
- |
Read only. Monitors DAVin |
1 |
RENoutMon |
- |
Readonly. Monitors RENout |
0 |
DAVoutMon |
- |
Read only. Monitors DAVout |
REG9 |
Function |
Default |
Description |
7 |
SampleDel1 |
1 |
Sample VREF delay |
6 |
SampleDel0 |
0 |
Sample VREF delay |
5 |
ClampDel1 |
1 |
Clamp Delay |
4 |
ClampDel0 |
0 |
Clamp Delay |
3 |
CompEn1 |
1 |
Comparator Enable Delay |
2 |
CompEn0 |
0 |
Comparator Enable Delay |
1 |
CompDel1 |
1 |
Comparator Output Delay |
0 |
CompDel0 |
0 |
Comparator Output Delay |
The following registers with addresses 10-21 control voltage biases/thresholds on the chip with 8 bit resolution. Values of 0-255 give corresponding ranges of 0.5V-2.5V. For some registers the values become inverted in holes mode. For examples register 10 controls the preamp bias. Loading this with 0 would give a voltage of 0.5V in electrons mode and 2.5V in holes mode.
Register Address |
Function |
Default |
Value Electrons |
Value Holes |
Description |
10 |
VPRE |
00001101 |
0.6V |
2.4V |
Preamp
Bias |
11 |
VSHA |
11110011 |
2.4V |
0.6V |
Shaper
Bias |
12 |
VPRE10 |
10000000 |
1.5V |
1.5V |
10x
Preamp Gain Bias |
13 |
VSHA10 |
10000000 |
1.5V |
1.5V |
10x
Shaper Gain Bias |
14 |
VTS |
01000000 |
1V |
2V |
Time
stamp Threshold |
15 |
VET |
11000000 |
2V |
1V |
Energy
Threshold |
16 |
VCALH |
10100000 |
1.75V |
1.75V |
High
Calibrate Voltage, Max 2V (11000000) |
17 |
VCALL |
01100000 |
1.25V |
1.25V |
Low
Calibrate Voltage, Min 1V (01000000) |
18 |
VREFL |
00000000 |
0.5V |
0.5V |
Low Reference |
19 |
VREFM |
10000000 |
1.5V |
1.5V |
Mid Reference |
20 |
VREFH |
11111111 |
2.5V |
2.5V |
High
Reference |
21 |
VLVDS |
01011001 |
1.2V |
1.2V |
LVDS
Common Mode |
|
|
|
|
|
|
The following registers with addresses 64-95 use single bit control of each channel to specify calibrates or power down.
Register Address |
Channels |
Function |
Default |
Description |
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 |
0-7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 64-71 72-79 80-87 88-95 96-103 104-111 112-119 120-127 |
CalChan |
0 |
Calibrate
Channels, 0=No, 1=Yes |
80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 |
0-7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 64-71 72-79 80-87 88-95 96-103 104-111 112-119 120-127 |
PwrDwn |
0 |
Power
Down Channels, 0=No, 1=Yes |
The following registers with addresses 128-255 can only be accessed by specifying the relevant page bit in REG0.
Page |
Register Address |
Channel |
Function |
Default |
Description |
0 |
128-255 |
0-127 |
PreAmpCmp |
00000000 |
Preamp Compensation Cap |
1 |
128-255 |
0-127 |
PreAmpAdj |
00000000 |
Preamp Feedback Offset |
2 |
128-255 |
0-127 |
10xPreAdj |
00000000 |
10x Preamp Gain Amp Offset |
3 |
128-255 |
0-127 |
10xShaAdj |
00000000 |
10x Shaper Gain Amp Offset |
In order to calibrate each channel it is necessary to inject some charge into the preamplifier input. This is done using the calibration controls. Firstly, it is necessary to programme which channels are going to be calibrated by programming the relevant bits in registers 64-79. Once this is done, the amplitude of the calibrate pulse must be programmed. This is done using registers 16 and 17. In addition the chip must be in calibrate mode (see 13.2). A pulse on the VAL input now controls the calibrate circuit.
Figure 16 shows the calibration controls. The calibrate block must be set up with the voltages VCALH and VCALL as described above. The pulse control comes from the VAL input in calibration control. The polarity of the voltage pulse CalOut is determined by whether the chip is in electrons or holes mode. The CalOut is applied to a 2.9pF capacitor and a charge is injected into the preamplifier.
2.9pF
Figure 16: Calibration
All LVDS inputs have internal termination except for the 200MHz clock and VAL inputs. All LVDS outputs require termination either internally when driving another R3B ASIC or externally when driving a DAQ. Figure 16 shows the LVDS driver, which is a standard switched current configuration. When terminated by 100W the output swing should be 350mV across the resistor. The common mode is 1.2V and is controlled using the VBIAS input which is programmable through I2C.
Figure 17: On-chip LVDS
Driver
The following table list all of the pads on the chip, their positions relative to the bottom left corner, the pad type and function. Note that some LVDS input pads have on-chip termination so do not require external termination. Also, some pads on the top and bottom edges of the chip can be turned off.
Pad |
Name |
X position |
Y position |
Chip Edge |
Pad Type |
Comment |
Function |
|
1 |
RENInP |
9922.1 |
420.2 |
Top |
LVDS Input |
Internal Termination |
Daisy Chain Read Enable |
|
2 |
RENInN |
10022.1 |
420.2 |
Top |
LVDS Input |
Can be disabled |
|
|
3 |
DAVOUTP |
10172.1 |
420.2 |
Top |
LVDS Output |
Daisy Chain Data Valid |
|
|
4 |
DAVOUTN |
10272.1 |
420.2 |
Top |
LVDS Output |
Can be disabled |
|
|
5 |
DataClkInP |
10422.1 |
420.2 |
Top |
LVDS Input |
Internal Termination |
Daisy Chain Clock In |
|
6 |
DataClkInN |
10522.1 |
420.2 |
Top |
LVDS Input |
Can be disabled |
|
|
7 |
DataInP |
10672.1 |
420.2 |
Top |
LVDS Input |
Internal Termination |
Daisy Chain Data |
|
8 |
DataInN |
10772.1 |
420.2 |
Top |
LVDS Input |
Can be disabled |
|
|
9 |
ToNeP1 |
10922.1 |
420.2 |
Top |
LVDS Output |
Hit To Neighbour 1 |
|
|
10 |
ToNeN1 |
11022.1 |
420.2 |
Top |
LVDS Output |
|
||
11 |
FrNeP1 |
11122.1 |
420.2 |
Top |
LVDS Input |
Internal Termination |
Hit From Neighbour 1 |
|
12 |
FrNeN1 |
11222.1 |
420.2 |
Top |
LVDS Input |
|
||
13 |
SDAIN |
11372.1 |
420.2 |
Top |
CMOS Input |
Routed across chip |
I2C Data In |
|
14 |
SDAOUT |
11472.1 |
420.2 |
Top |
Open Drain |
Routed across chip |
I2C Data Out |
|
15 |
SCLK |
11572.1 |
420.2 |
Top |
CMOS Input |
Routed across chip |
I2C Clock |
|
16 |
VDDD |
12812.6 |
76.75 |
Back |
Supply |
3.3V / 0.05A |
Digital Supply |
Pads wider than version 1 ASIC |
17 |
GNDD |
12812.6 |
223.250 |
Back |
Supply |
0V / 0.05A |
Digital Ground |
|
18 |
GNDA |
12812.6 |
449.75 |
Back |
Supply |
0V / 0.25A |
Analogue Ground |
Merged into 1 pad |
19 |
||||||||
20 |
VDDA |
12812.6 |
749.75 |
Back |
Supply |
3.3V / 0.25A |
Analogue Supply |
Merged into 1 pad |
21 |
||||||||
22 |
HitOr128P |
12812.6 |
1000 |
Back |
Current |
0-2mA |
128 Channel OR of Hits |
|
23 |
not used |
12812.6 |
1100 |
- |
- |
Require 50Rr |
|
|
24 |
VALP |
12812.6 |
1200 |
Back |
LVDS Input |
Require External |
Validate/Test/Sync |
|
25 |
VALN |
12812.6 |
1300 |
Back |
LVDS Input |
100R Termination |
|
|
26 |
RESET |
12812.6 |
1440 |
Back |
CMOS Input |
Active High |
Reset |
|
27 |
CLKP |
12812.6 |
1590 |
Back |
LVDS Input |
Require External |
Timestamp clock |
|
28 |
CLKN |
12812.6 |
1690 |
Back |
LVDS Input |
100R Termination |
|
|
29 |
DataIn1P |
12812.6 |
1890 |
Back |
LVDS Input |
Internal Termination |
Daisy Chain Data In1 |
|
30 |
DataIn1N |
12812.6 |
1990 |
Back |
LVDS Input |
50Mbit/s |
|
|
31 |
DataClkIn1P |
12812.6 |
2090 |
Back |
LVDS Input |
Internal Termination |
Daisy Chain Clock
In1 |
|
32 |
DataClkIn1N |
12812.6 |
2190 |
Back |
LVDS Input |
50MHz |
|
|
33 |
GNDA |
12812.6 |
2439.8 |
Back |
Supply |
Analogue Ground |
Merged into 1 pad |
|
34 |
||||||||
35 |
||||||||
36 |
DAVOut1P |
12812.6 |
2690 |
Back |
LVDS Output |
Daisy Chain |
|
|
37 |
DAVOut1N |
12812.6 |
2790 |
Back |
LVDS Output |
Data Valid Out 1 |
|
|
38 |
RENIn1P |
12812.6 |
2890 |
Back |
LVDS Input |
Internal Termination |
Daisy Chain |
|
39 |
RENIn1N |
12812.6 |
2990 |
Back |
LVDS Input |
Read Enable In 1 |
|
|
40 |
VDDA |
12812.6 |
3239.8 |
Back |
Supply |
Analogue Supply |
Merged into 1 pad |
|
41 |
||||||||
42 |
||||||||
43 |
RENOut1N |
12812.6 |
3490 |
Back |
LVDS Output |
Daisy Chain |
|
|
44 |
RENOut1P |
12812.6 |
3590 |
Back |
LVDS Output |
Read Enable Out 1 |
|
|
45 |
DAVIn1N |
12812.6 |
3690 |
Back |
LVDS Input |
Internal Termination |
Daisy Chain |
|
46 |
DAVIn1P |
12812.6 |
3790 |
Back |
LVDS Input |
Data Valid In 1 |
|
|
47 |
Ifdb |
12812.6 |
3940 |
Back |
Passive |
Current biases |
|
|
48 |
Icmp |
12812.6 |
4040 |
Back |
Passive |
|
||
49 |
Iamp |
12812.6 |
4140 |
Back |
Passive |
|
||
50 |
DataClkOut1N |
12812.6 |
4330 |
Back |
LVDS Output |
Daisy Chain Clock Out 1 |
|
|
51 |
DataClkOut1P |
12812.6 |
4430 |
Back |
LVDS Output |
|
||
52 |
DataOut1N |
12812.6 |
4530 |
Back |
LVDS Output |
Daisy Chain Data Out 1 |
|
|
53 |
DataOut1P |
12812.6 |
4630 |
Back |
LVDS Output |
|
||
54 |
ADDR4 |
12812.6 |
4830 |
Back |
Input |
Uses 3 voltage level coding |
Board Address |
|
55 |
ADDR5 |
12812.6 |
4930 |
Back |
Input |
VDD / 0.5*VDD/ GND |
|
|
56 |
ADDR6 |
12812.6 |
5030 |
Back |
Input |
|
||
57 |
ADDR7 |
12812.6 |
5130 |
Back |
Input |
|
||
58 |
VDDA |
12812.6 |
5399.75 |
Back |
Supply |
3.3V / 0.25A |
Analogue Supply |
Merged into 1 pad |
59 |
||||||||
60 |
GNDA |
12812.6 |
5699.75 |
Back |
Supply |
0V / 0.25A |
Analogue Ground |
Merged Into 1 pad |
61 |
||||||||
62 |
GNDD |
12812.6 |
5926.2 |
Back |
Supply |
0V / 0.05A |
Digital Ground |
Pads wider than version 1 ASIC |
63 |
VDDD |
12812.6 |
6073.2 |
Back |
Supply |
0V / 0.05A |
Digital Supply |
|
64 |
SCLK |
11572.1 |
5729.8 |
Bottom |
CMOS Input |
Routed across chip |
I2C Clock |
|
65 |
SDAOUT |
11472.1 |
5729.8 |
Bottom |
Open Drain |
Routed across chip |
I2C Data out |
|
66 |
SDAIN |
11372.1 |
5729.8 |
Bottom |
CMOS Input |
Routed across chip |
I2C Data In |
|
67 |
ToNeN2 |
11222.1 |
5729.8 |
Bottom |
LVDS Output |
Hit To Neighbour 2 |
|
|
68 |
ToNeP2 |
11122.1 |
5729.8 |
Bottom |
LVDS Output |
|
||
69 |
FrNeN2 |
11022.1 |
5729.8 |
Bottom |
LVDS Input |
Internal Termination |
Hit From Neighbour 2 |
|
70 |
FrNeP2 |
10922.1 |
5729.8 |
Bottom |
LVDS Input |
|
||
71 |
DataOutN |
10772.1 |
5729.8 |
Bottom |
LVDS Output |
Daisy Chain Data Out |
|
|
72 |
DataOutP |
10672.1 |
5729.8 |
Bottom |
LVDS Output |
Can be disabled |
|
|
73 |
DataClkOutN |
10522.1 |
5729.8 |
Bottom |
LVDS Output |
Daisy Chain Clock Out |
|
|
74 |
DataClkOutP |
10422.1 |
5729.8 |
Bottom |
LVDS Output |
Can be disabled |
|
|
75 |
DAVInN |
10272.1 |
5729.8 |
Bottom |
LVDS Input |
Internal Termination |
Daisy Chain Data Valid In |
|
76 |
DAVINP |
10172.1 |
5729.8 |
Bottom |
LVDS Input |
Can be disabled |
|
|
77 |
RENOutN |
10022.1 |
5729.8 |
Bottom |
LVDS Output |
Daisy Chain Read Enable |
|
|
78 |
RENOutP |
9922.1 |
5729.8 |
Bottom |
LVDS Output |
Can be disabled |
|
|
79 |
ADDR<0> |
11089 |
4820.3 |
Internal |
CMOS Input |
Chip Address Bit 0 |
|
|
80 |
ADDR<1> |
11089 |
4920.5 |
Internal |
CMOS Input |
Chip Address Bit 1 |
|
|
81 |
ADDR<2> |
11089 |
5020.1 |
Internal |
CMOS Input |
Chip Address Bit 2 |
|
|
82 |
ADDR<3> |
11089 |
5120.3 |
Internal |
CMOS Input |
Chip Address Bit 3 |
|
|
83 |
PullUp |
10091.75 |
4820.35 |
Internal |
3.3V |
Used for Address |
Pull Up |
|
84 |
PullUp |
10091.75 |
4920.55 |
Internal |
3.3V |
Used for Address |
Pull Up |
|
85 |
PullUp |
10091.75 |
5020.15 |
Internal |
3.3V |
Used for Address |
Pull Up |
|
86 |
PullUp |
10091.75 |
5120.35 |
Internal |
3.3V |
Used for Address |
Pull Up |
|
87 |
ADCtest
|
11074.4 |
3171.4 |
Internal |
Analogue Input |
ADC Test Input |
|
|
88 |
In<0> |
170.85 |
5868.9 |
Internal |
Analogue |
Channel Input |
|
|
89 |
In<1> |
380.85 |
5824.9 |
Front |
Analogue |
Channel Input |
|
|
90 |
In<2> |
170.85 |
5780.9 |
Front |
Analogue |
Channel Input |
|
|
91 |
In<3> |
380.85 |
5736.9 |
Front |
Analogue |
Channel Input |
|
|
92 |
In<4> |
170.85 |
5692.9 |
Front |
Analogue |
Channel Input |
|
|
93 |
In<5> |
380.85 |
5648.9 |
Front |
Analogue |
Channel Input |
|
|
94 |
In<6> |
170.85 |
5604.9 |
Front |
Analogue |
Channel Input |
|
|
95 |
In<7> |
380.85 |
5560.9 |
Front |
Analogue |
Channel Input |
|
|
96 |
In<8> |
170.85 |
5516.9 |
Front |
Analogue |
Channel Input |
|
|
97 |
In<9> |
380.85 |
5472.9 |
Front |
Analogue |
Channel Input |
|
|
98 |
In<10> |
170.85 |
5428.9 |
Front |
Analogue |
Channel Input |
|
|
99 |
In<11> |
380.85 |
5384.9 |
Front |
Analogue |
Channel Input |
|
|
100 |
In<12> |
170.85 |
5340.9 |
Front |
Analogue |
Channel Input |
|
|
101 |
In<13> |
380.85 |
5296.9 |
Front |
Analogue |
Channel Input |
|
|
102 |
In<14> |
170.85 |
5252.9 |
Front |
Analogue |
Channel Input |
|
|
103 |
In<15> |
380.85 |
5208.9 |
Front |
Analogue |
Channel Input |
|
|
104 |
In<16> |
170.85 |
5164.9 |
Front |
Analogue |
Channel Input |
|
|
105 |
In<17> |
380.85 |
5120.9 |
Front |
Analogue |
Channel Input |
|
|
106 |
In<18> |
170.85 |
5076.9 |
Front |
Analogue |
Channel Input |
|
|
107 |
In<19> |
380.85 |
5032.9 |
Front |
Analogue |
Channel Input |
|
|
108 |
In<20> |
170.85 |
4988.9 |
Front |
Analogue |
Channel Input |
|
|
109 |
In<21> |
380.85 |
4944.9 |
Front |
Analogue |
Channel Input |
|
|
110 |
In<22> |
170.85 |
4900.9 |
Front |
Analogue |
Channel Input |
|
|
111 |
In<23> |
380.85 |
4856.9 |
Front |
Analogue |
Channel Input |
|
|
112 |
In<24> |
170.85 |
4812.9 |
Front |
Analogue |
Channel Input |
|
|
113 |
In<25> |
380.85 |
4768.9 |
Front |
Analogue |
Channel Input |
|
|
114 |
In<26> |
170.85 |
4724.9 |
Front |
Analogue |
Channel Input |
|
|
115 |
In<27> |
380.85 |
4680.9 |
Front |
Analogue |
Channel Input |
|
|
116 |
In<28> |
170.85 |
4636.9 |
Front |
Analogue |
Channel Input |
|
|
117 |
In<29> |
380.85 |
4592.9 |
Front |
Analogue |
Channel Input |
|
|
118 |
In<30> |
170.85 |
4548.9 |
Front |
Analogue |
Channel Input |
|
|
119 |
In<31> |
380.85 |
4504.9 |
Front |
Analogue |
Channel Input |
|
|
120 |
In<32> |
170.85 |
4460.9 |
Front |
Analogue |
Channel Input |
|
|
121 |
In<33> |
380.85 |
4416.9 |
Front |
Analogue |
Channel Input |
|
|
122 |
In<34> |
170.85 |
4372.9 |
Front |
Analogue |
Channel Input |
|
|
123 |
In<35> |
380.85 |
4328.9 |
Front |
Analogue |
Channel Input |
|
|
124 |
In<36> |
170.85 |
4284.9 |
Front |
Analogue |
Channel Input |
|
|
125 |
In<37> |
380.85 |
4240.9 |
Front |
Analogue |
Channel Input |
|
|
126 |
In<38> |
170.85 |
4196.9 |
Front |
Analogue |
Channel Input |
|
|
127 |
In<39> |
380.85 |
4152.9 |
Front |
Analogue |
Channel Input |
|
|
128 |
In<40> |
170.85 |
4108.9 |
Front |
Analogue |
Channel Input |
|
|
129 |
In<41> |
380.85 |
4064.9 |
Front |
Analogue |
Channel Input |
|
|
130 |
In<42> |
170.85 |
4020.9 |
Front |
Analogue |
Channel Input |
|
|
131 |
In<43> |
380.85 |
3976.9 |
Front |
Analogue |
Channel Input |
|
|
132 |
In<44> |
170.85 |
3932.9 |
Front |
Analogue |
Channel Input |
|
|
133 |
In<45> |
380.85 |
3888.9 |
Front |
Analogue |
Channel Input |
|
|
134 |
In<46> |
170.85 |
3844.9 |
Front |
Analogue |
Channel Input |
|
|
135 |
In<47> |
380.85 |
3800.9 |
Front |
Analogue |
Channel Input |
|
|
136 |
In<48> |
170.85 |
3756.9 |
Front |
Analogue |
Channel Input |
|
|
137 |
In<49> |
380.85 |
3712.9 |
Front |
Analogue |
Channel Input |
|
|
138 |
In<50> |
170.85 |
3668.9 |
Front |
Analogue |
Channel Input |
|
|
139 |
In<51> |
380.85 |
3624.9 |
Front |
Analogue |
Channel Input |
|
|
140 |
In<52> |
170.85 |
3580.9 |
Front |
Analogue |
Channel Input |
|
|
141 |
In<53> |
380.85 |
3536.9 |
Front |
Analogue |
Channel Input |
|
|
142 |
In<54> |
170.85 |
3492.9 |
Front |
Analogue |
Channel Input |
|
|
143 |
In<55> |
380.85 |
3448.9 |
Front |
Analogue |
Channel Input |
|
|
144 |
In<56> |
170.85 |
3404.9 |
Front |
Analogue |
Channel Input |
|
|
145 |
In<57> |
380.85 |
3360.9 |
Front |
Analogue |
Channel Input |
|
|
146 |
In<58> |
170.85 |
3316.9 |
Front |
Analogue |
Channel Input |
|
|
147 |
In<59> |
380.85 |
3272.9 |
Front |
Analogue |
Channel Input |
|
|
148 |
In<60> |
170.85 |
3228.9 |
Front |
Analogue |
Channel Input |
|
|
149 |
In<61> |
380.85 |
3184.9 |
Front |
Analogue |
Channel Input |
|
|
150 |
In<62> |
170.85 |
3140.9 |
Front |
Analogue |
Channel Input |
|
|
151 |
In<63> |
380.85 |
3096.9 |
Front |
Analogue |
Channel Input |
|
|
152 |
In<64> |
170.85 |
3052.9 |
Front |
Analogue |
Channel Input |
|
|
153 |
In<65> |
380.85 |
3008.9 |
Front |
Analogue |
Channel Input |
|
|
154 |
In<66> |
170.85 |
2964.9 |
Front |
Analogue |
Channel Input |
|
|
155 |
In<67> |
380.85 |
2920.9 |
Front |
Analogue |
Channel Input |
|
|
156 |
In<68> |
170.85 |
2876.9 |
Front |
Analogue |
Channel Input |
|
|
157 |
In<69> |
380.85 |
2832.9 |
Front |
Analogue |
Channel Input |
|
|
158 |
In<70> |
170.85 |
2788.9 |
Front |
Analogue |
Channel Input |
|
|
159 |
In<71> |
380.85 |
2744.9 |
Front |
Analogue |
Channel Input |
|
|
160 |
In<72> |
170.85 |
2700.9 |
Front |
Analogue |
Channel Input |
|
|
161 |
In<73> |
380.85 |
2656.9 |
Front |
Analogue |
Channel Input |
|
|
162 |
In<74> |
170.85 |
2612.9 |
Front |
Analogue |
Channel Input |
|
|
163 |
In<75> |
380.85 |
2568.9 |
Front |
Analogue |
Channel Input |
|
|
164 |
In<76> |
170.85 |
2524.9 |
Front |
Analogue |
Channel Input |
|
|
165 |
In<77> |
380.85 |
2480.9 |
Front |
Analogue |
Channel Input |
|
|
166 |
In<78> |
170.85 |
2436.9 |
Front |
Analogue |
Channel Input |
|
|
167 |
In<79> |
380.85 |
2392.9 |
Front |
Analogue |
Channel Input |
|
|
168 |
In<80> |
170.85 |
2348.9 |
Front |
Analogue |
Channel Input |
|
|
169 |
In<81> |
380.85 |
2304.9 |
Front |
Analogue |
Channel Input |
|
|
170 |
In<82> |
170.85 |
2260.9 |
Front |
Analogue |
Channel Input |
|
|
171 |
In<83> |
380.85 |
2216.9 |
Front |
Analogue |
Channel Input |
|
|
172 |
In<84> |
170.85 |
2172.9 |
Front |
Analogue |
Channel Input |
|
|
173 |
In<85> |
380.85 |
2128.9 |
Front |
Analogue |
Channel Input |
|
|
174 |
In<86> |
170.85 |
2084.9 |
Front |
Analogue |
Channel Input |
|
|
175 |
In<87> |
380.85 |
2040.9 |
Front |
Analogue |
Channel Input |
|
|
176 |
In<88> |
170.85 |
1996.9 |
Front |
Analogue |
Channel Input |
|
|
177 |
In<89> |
380.85 |
1952.9 |
Front |
Analogue |
Channel Input |
|
|
178 |
In<90> |
170.85 |
1908.9 |
Front |
Analogue |
Channel Input |
|
|
179 |
In<91> |
380.85 |
1864.9 |
Front |
Analogue |
Channel Input |
|
|
180 |
In<92> |
170.85 |
1820.9 |
Front |
Analogue |
Channel Input |
|
|
181 |
In<93> |
380.85 |
1776.9 |
Front |
Analogue |
Channel Input |
|
|
182 |
In<94> |
170.85 |
1732.9 |
Front |
Analogue |
Channel Input |
|
|
183 |
In<95> |
380.85 |
1688.9 |
Front |
Analogue |
Channel Input |
|
|
184 |
In<96> |
170.85 |
1644.9 |
Front |
Analogue |
Channel Input |
|
|
185 |
In<97> |
380.85 |
1600.9 |
Front |
Analogue |
Channel Input |
|
|
186 |
In<98> |
170.85 |
1556.9 |
Front |
Analogue |
Channel Input |
|
|
187 |
In<99> |
380.85 |
1512.9 |
Front |
Analogue |
Channel Input |
|
|
188 |
In<100> |
170.85 |
1468.9 |
Front |
Analogue |
Channel Input |
|
|
189 |
In<101> |
380.85 |
1424.9 |
Front |
Analogue |
Channel Input |
|
|
190 |
In<102> |
170.85 |
1380.9 |
Front |
Analogue |
Channel Input |
|
|
191 |
In<103> |
380.85 |
1336.9 |
Front |
Analogue |
Channel Input |
|
|
192 |
In<104> |
170.85 |
1292.9 |
Front |
Analogue |
Channel Input |
|
|
193 |
In<105> |
380.85 |
1248.9 |
Front |
Analogue |
Channel Input |
|
|
194 |
In<106> |
170.85 |
1204.9 |
Front |
Analogue |
Channel Input |
|
|
195 |
In<107> |
380.85 |
1160.9 |
Front |
Analogue |
Channel Input |
|
|
196 |
In<108> |
170.85 |
1116.9 |
Front |
Analogue |
Channel Input |
|
|
197 |
In<109> |
380.85 |
1072.9 |
Front |
Analogue |
Channel Input |
|
|
198 |
In<110> |
170.85 |
1028.9 |
Front |
Analogue |
Channel Input |
|
|
199 |
In<111> |
380.85 |
984.9 |
Front |
Analogue |
Channel Input |
|
|
200 |
In<112> |
170.85 |
940.9 |
Front |
Analogue |
Channel Input |
|
|
201 |
In<113> |
380.85 |
896.9 |
Front |
Analogue |
Channel Input |
|
|
202 |
In<114> |
170.85 |
852.9 |
Front |
Analogue |
Channel Input |
|
|
203 |
In<115> |
380.85 |
808.9 |
Front |
Analogue |
Channel Input |
|
|
204 |
In<116> |
170.85 |
764.9 |
Front |
Analogue |
Channel Input |
|
|
205 |
In<117> |
380.85 |
720.9 |
Front |
Analogue |
Channel Input |
|
|
206 |
In<118> |
170.85 |
676.9 |
Front |
Analogue |
Channel Input |
|
|
207 |
In<119> |
380.85 |
632.9 |
Front |
Analogue |
Channel Input |
|
|
208 |
In<120> |
170.85 |
588.9 |
Front |
Analogue |
Channel Input |
|
|
209 |
In<121> |
380.85 |
544.9 |
Front |
Analogue |
Channel Input |
|
|
210 |
In<122> |
170.85 |
500.9 |
Front |
Analogue |
Channel Input |
|
|
211 |
In<123> |
380.85 |
456.9 |
Front |
Analogue |
Channel Input |
|
|
212 |
In<124> |
170.85 |
412.9 |
Front |
Analogue |
Channel Input |
|
|
213 |
In<125> |
380.85 |
368.9 |
Front |
Analogue |
Channel Input |
|
|
214 |
In<126> |
170.85 |
324.9 |
Front |
Analogue |
Channel Input |
|
|
215 |
In<127> |
380.85 |
280.9 |
Front |
Analogue |
Channel Input |
|
|
|
|
|
|
|
|
|
|
|
The chip is 12918umx6150um in size (not including any scribe channel that may be left after dicing).
Actual
die sizes may vary due to wafer sawing.