Figure 9 shows the peak hold circuit in holes mode. The signal Rst initialises the circuit by discharging
the capacitor C PH . With SampleB on and Sample off, the voltage V PH follows the signal from the
shaper. A small trickle current is present while the signal remains below the energy threshold
(controlled by HitB ). This ensures that when there are no signals present for a long time the peak
hold circuit does not drift. Once the signal is above threshold the trickle current switches off and the
circuit acts as a standard peak hold. A predetermined time after the voltage has peaked, the Sample
signal switches on (and SampleB off) to sample the voltage on C SH where it is buffered by the second
amplifier on to the analogue multiplexer. Figure 10 shows a the signals operating in a typical readout
cycle.
V S H A
V P H
V O U T
Hit
Sample
Rst
Figure 10: Peak Hold Operation
8 Analogue Multiplexer
The analogue mutliplexer is comprised of 128 complementary switches connecting the output of
each peak hold to a common node. It is controlled by the channel readout logic.
9 Digital Multiplexer
The digital multiplexer is comprised of tristate buffers. It connects the 7 channel addresses,15
timestamps bits and the "hit" bit from each channel onto common bus nodes.
11