Each channel of the ASIC consists of a charge sensitive Preamplifier, Shaper, Peak Hold, Gain
Amplifiers, Comparators and Control Logic. The remaining chip functionality consists of an Analogue
Miultiplexer, ADC, Data Buffer, 128 bit OR, Timestamp Counter, Control Logic and I2C Interface and
Registers.
The preamplifiers remove most of any signal charge from any detector strips which are hit by
ionising particles. These charges are integrated onto the feedback capacitors of the preamplifiers
into a voltage signal proportional to the energy of the ionising particles which generated the charge.
These voltages are then filtered by the CR-RC shapers to reduce noise and generate output pulses
which feed into th peak hold circuits where the signal amplitudes are saved prior to digitisation with
a 12 bit successive approximation register ADC
There are two comparators in each channel, one connected to an amplified version of the
preamplifier output, and the other connected to an amplified version of the shaper output. The
former is used to generate a timestamp and the latter used to generate minimum energy threshold
below which no signals are read out. Any signal above the energy threshold is a "hit" and this also
triggers the readout of any neighbouring channels. An analogue multiplexer outputs the voltage
from each hit channel to the ADC where it is converted to 12 bits. Each channel is dynamically reset
once the signal has been saved.
Channel control logic sequences the resets, determines which channels require reading out and
latches the timestamp. Digital data output from each hit channel includes the 15 bit timestamp and
7 bit channel address. An additional bit indicates whether the timestamp is valid.
Multiple chips are daisy-chained together with one chip acting as a master and the others as slaves.
The master chips detects whether data is available to be read out and then each hit chip outputs a
set number of data frames before passing the token on to the next chip. A 32 deep data buffer holds
the channel data for each hit until it can be read off chip. Control logic sequences the readout and
controls the daisy chaining.
An additional output from the ASIC is a 128 bit OR of all the hit channels which can be used as a
trigger.
2 Preamplifier
A diagram of the preamplifier operating in Electrons mode is shown in figure 2. The preamplifier is
comprised of a differential amplifier with one input biased to a programmable voltage and the other
input connected to one strip of the detector. A capacitor connects in negative feedback between the
output of the preamplifier and the input connected to the detector. Thus any charge generated on
the detector strip is removed by the preamplifier and integrated on the feedback capacitor. The
voltage generated at the output of the preamplifier is proportional to the charge. The dynamic range
of the preamplifier is 50MeV. The lowest energy that will be measured is about 40keV so the noise
level of the full channel including the preamplifier should be about 8keV.
The preamplifier is DC connected to the detector strip, so any leakage current present in the
detector will get integrated on the feedback capacitor and will push the preamplifier into saturation.
3