76
96-103
77
104-111
78
112-119
79
120-127
80
0-7
PwrDwn
0
Power Down Channels, 0=No, 1=Yes
81
8-15
82
16-23
83
24-31
84
32-39
85
40-47
86
48-55
87
56-63
88
64-71
89
72-79
90
80-87
91
88-95
92
96-103
93
104-111
94
112-119
95
120-127
16.4.2 Paged Registers
The following registers with addresses 128-255 can only be accessed by specifying the relevant page
bit in REG0.
Page
Register
Channel
Function
Default
Description
Address
0
128-255
0-127
PreAmpCmp
00000000
Preamp Compensation Cap
1
128-255
0-127
PreAmpAdj
00000000
Preamp Feedback Offset
2
128-255
0-127
10xPreAdj
00000000
10x Preamp Gain Amp Offset
3
128-255
0-127
10xShaAdj
00000000
10x Shaper Gain Amp Offset
17 Calibration
In order to calibrate each channel it is necessary to inject some charge into the preamplifier input.
This is done using the calibration controls. Firstly, it is necessary to programme which channels are
going to be calibrated by programming the relevant bits in registers 64-79. Once this is done, the
amplitude of the calibrate pulse must be programmed. This is done using registers 16 and 17. In
addition the chip must be in calibrate mode (see 13.2). A pulse on the VAL input now controls the
calibrate circuit.
Figure 16 shows the calibration controls. The calibrate block must be set up with the voltages VCALH
and VCALL as described above. The pulse control comes from the VAL input in calibration control.
The polarity of the voltage pulse CalOut is determined by whether the chip is in electrons or holes
mode. The CalOut is applied to a 1.1pF capacitor and a charge is injected into the preamplifier.
20