43
RENOut1N
12812.6
3490
Back
LVDS Output
Daisy Chain
44
RENOut1P
12812.6
3590
Back
LVDS Output
Read Enable Out 1
45
DAVIn1N
12812.6
3690
Back
LVDS Input
Internal Termination
Daisy Chain
46
DAVIn1P
12812.6
3790
Back
LVDS Input
Data Valid In 1
47
Ifdb
12812.6
3940
Back
Passive
Current biases
48
Icmp
12812.6
4040
Back
Passive
49
Iamp
12812.6
4140
Back
Passive
50
DataClkOut1N
12812.6
4330
Back
LVDS Output
Daisy Chain Clock Out 1
51
DataClkOut1P
12812.6
4430
Back
LVDS Output
52
DataOut1N
12812.6
4530
Back
LVDS Output
Daisy Chain Data Out 1
53
DataOut1P
12812.6
4630
Back
LVDS Output
54
ADDR4
12812.6
4830
Back
Input
Uses 3 voltage level
Board Address
coding
55
ADDR5
12812.6
4930
Back
Input
VDD / 0.5*VDD/ GND
56
ADDR6
12812.6
5030
Back
Input
57
ADDR7
12812.6
5130
Back
Input
58
VDDA
12812.6
5350
Back
Supply
3.3V / 0.25A
Analogue Supply
59
VDDA
12812.6
5450
Back
Supply
3.3V / 0.25A
60
GNDA
12812.6
5650
Back
Supply
0V / 0.25A
Analogue Ground
61
GNDA
12812.6
5750
Back
Supply
0V / 0.25A
62
GNDD
12812.6
5950
Back
Supply
0V / 0.05A
Digital Ground
63
VDDD
12812.6
6050
Back
Supply
0V / 0.05A
Digital Supply
64
SCLK
11572.1
5729.8
Bottom
CMOS Input
Routed across chip
I2C Clock
65
SDAOUT
11472.1
5729.8
Bottom
Open Drain
Routed across chip
I2C Data out
66
SDAIN
11372.1
5729.8
Bottom
Output
Routed across chip
I2C Data In
67
ToNeN2
11222.1
5729.8
Bottom
Input
Hit To Neighbour 2
68
ToNeP2
11122.1
5729.8
Bottom
LVDS Output
69
FrNeN2
11022.1
5729.8
Bottom
LVDS Output
Internal Termination
Hit From Neighbour 2
70
FrNeP2
10922.1
5729.8
Bottom
LVDS Input
71
DataOutN
10772.1
5729.8
Bottom
LVDS Input
Daisy Chain Data Out
72
DataOutP
10672.1
5729.8
Bottom
LVDS Output
Can be disabled
73
DataClkOutN
10522.1
5729.8
Bottom
LVDS Output
Daisy Chain Clock Out
74
DataClkOutP
10422.1
5729.8
Bottom
LVDS Output
Can be disabled
75
DAVInN
10272.1
5729.8
Bottom
LVDS Output
Internal Termination
Daisy Chain Data Valid In
76
DAVINP
10172.1
5729.8
Bottom
LVDS Input
Can be disabled
77
RENOutN
10022.1
5729.8
Bottom
LVDS Input
Daisy Chain Read Enable
78
RENOutP
9922.1
5729.8
Bottom
LVDS Output
Can be disabled
79
ADDR<0>
11089
4820.3
Internal
LVDS Output
Chip Address Bit 0
80
ADDR<1>
11089
4920.5
Internal
CMOS Input
Chip Address Bit 1
81
ADDR<2>
11089
5020.1
Internal
CMOS Input
Chip Address Bit 2
82
ADDR<3>
11089
5120.3
Internal
CMOS Input
Chip Address Bit 3
83
PullUp
10091.75
4820.35
Internal
CMOS Input
Used for Address
Pull Up
84
PullUp
10091.75
4920.55
Internal
3.3V
Used for Address
Pull Up
85
PullUp
10091.75
5020.15
Internal
3.3V
Used for Address
Pull Up
86
PullUp
10091.75
5120.35
Internal
3.3V
Used for Address
Pull Up
24