0
SDel0
0
Delay after Peak bit 0
REG5
Function
Default
Description
7
NPD7
1
Number of Data Packets bit 7
6
NPD6
0
Number of Data Packets bit 6
5
NPD5
0
Number of Data Packets bit 5
4
NPD4
0
Number of Data Packets bit 4
3
NPD3
0
Number of Data Packets bit 3
2
NPD2
0
Number of Data Packets bit 2
1
NPD1
0
Number of Data Packets bit 1
0
NPD0
0
Number of Data Packets bit 0
The following registers with addresses 10-21 control voltage biases/thresholds on the chip with 8 bit
resolution. Values of 0-255 give corresponding ranges of 0.5V-2.5V. For some registers the values
become inverted in holes mode. For examples register 10 controls the preamp bias. Loading this
with 0 would give a voltage of 0.5V in electrons mode and 2.5V in holes mode.
Register Function Default
Value
Value
Description
Address
Electrons
Holes
10
VPRE
00001101
0.6V
2.4V
Preamp Bias
11
VSHA
11110011
2.4V
0.6V
Shaper Bias
12
VPRE10
10000000
1.5V
1.5V
10x Preamp Gain Bias
13
VSHA10
10000000
1.5V
1.5V
10x Shaper Gain Bias
14
VTS
01000000
1V
2V
Time stamp Threshold
15
VET
11000000
2V
1V
Energy Threshold
16
VCALH
10100000
1.75V
1.75V
High Calibrate Voltage, Max 2V (11000000)
17
VCALL
01100000
1.25V
1.25V
Low Calibrate Voltage, Min 1V (01000000)
18
VREFL
00000000
0.5V
0.5V
Low Reference
19
VREFM
10000000
1.5V
1.5V
Mid Reference
20
VREFH
11111111
2.5V
2.5V
High Reference
21
VLVDS
01011001
1.2V
1.2V
LVDS Common Mode
The following registers with addresses 64-95 use single bit control of each channel to specify
calibrates or power down.
Register Address
Channels
Function
Default
Description
64
0-7
CalChan
0
Calibrate Channels, 0=No, 1=Yes
65
8-15
66
16-23
67
24-31
68
32-39
69
40-47
70
48-55
71
56-63
72
64-71
73
72-79
74
80-87
75
88-95
19