Figure 11 shows the timing of the channel readout logic. A hit occurs asynchronously in a particular
channel at time (0). On the next rising edge of the clock (1) the hit is detected by the state machine
and it begins sequencing the readout into the sample and hold circuit. Depending on the particular
shaping time the data must be sampled after the shaper output has peaked, with the peak being
held on the peak hold circuit. The time at which sampling starts (2) is therefore programmable with
minimum separation from (1) being 2 clock cycles.
Once the channel has been sampled it can be reset. All resets come on simultaneously, but are
sequenced to switch off as follows. Preamplifier after 2 clock cycles, Shaper after 3 clock cycles, Peak
Hold and channel logic after 4 clock cycles plus a programmable number of clock cycles.
11 Analogue-to-Digital Converter
The ASIC has one 12 bit successive approximation ADC. The ADC continuously runs at a rate of 1M
Sample/s. When its output contains hit data it is written into the data buffer to await readout. The
ADC also has a test mode where the input sample and hold buffer can be bypassed and a signal
applied directly into the ADC from an addition bondpad. This function is controlled by a bit in a
control register.
12 Data Buffer
The data buffer is a 48bit wide 32 deep FIFO. It stores the following data per hit while they are
waiting to be read out:
7 bit channel address
15 bit timestamp
1 bit hit
12 bit ADC data
13 Chip Control Logic
The chip control logic performms several functions.
13.1 Clocks
The ASIC can run off a 100MHz or a 200MHz input clock whilst, the data is read off at a rate of
50Mbits/s and the ADC runs at 1Msample/s. The clock block generates the 50Mhz clock from the
100MHz or 200MHz input clock. A prgorammable register bit defines whether the input clock being
used is either 100MHz or 200MHz. The 1MHz clock is generated from the 50MHz clock. For the case
of daisy chained chips, another control bit determines whether the internally generated 50MHz
clock is used (master chip) or whether it accepts an externally generated 50MHz clock (slave chip).
13.2 VAL Modes
The VAL input has 3 functions. which are determined by setting the relevent bits in a control
register.
13