1.41pF
Feedback Capacitor
VCALH (Max 2V)
1.1pF
VCALL (Min 1V)
Calibrate
CalOut
Block
In Channel
PULSE
Preamp
Calibrate
Capacitor
PreOut
VPRE
Pulse
CalOut
Electrons
PreOut
Mode
Electrons
CalOut
Holes
PreOut
Mode
Holes
Figure 16: Calibration
18 LVDS
All LVDS inputs have internal termination except for the 200MHz clock and VAL inputs. All LVDS
outputs require termination either internally when driving another R3B ASIC or externally when
driving a DAQ. Figure 16 shows the LVDS driver, which is a standard switched current configuration.
When terminated by 100 the output swing should be 350mV across the resistor. The common
mode is 1.2V and is controlled using the VBIAS input which is programmable through I2C.
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