10 Channel Readout Logic.
The Channel Readout Logic has 4 main functions:
Firstly, it detects when a channel has been hit and sequences the sampling of the data at the output
of the peak hold circuit. This has to be done once the Shaper has peaked, and to ensure this the
sampling time is programmable.
The second function of the logic is to control the resetting of the channels once the data has been
sampled. The Preamp, Shaper and 10xGain amps have a fixed reset length, however, the length of
time that the peak hold reset is held on is programmable using a 4 bit register.
The third function is to read out the data from channels which have been hit. The latched hit signals
from all channels are ORed together to determine whether there is any data to read out. If there is, a
shift register is initialised, which shifts down from channel 0 to channel 127, stopping in those
channels with data to read out, and skipping those channel which have nothing. It returns to its
waiting state if there is nothing else to read out or repeatedly cycles around the channels until there
is nothing left. The rate at which it does this is 1MHz. Data output from the channel include the
timestamp and channel address. The analogue output from the channel is passed to a multiplexer.
The last function of the channel readout logic is to generate a "trigger signal" which can be
transmitted off chip. A pulse is generated within each channel when the preamplifier comparator
fires.. The leading edge of the pulse is synchronous to the comparator signal, whilst the trailing edge
is synchronised to the clock. The length of this pulse is programmable using a 4 bit register. An 128
bit OR of all these trigger pulses is transmitted off chip.
10.1 Timing
Shaper
Output
Hit occurs here
(0)
1MHZ Clk
Hit synchronised here
Sample
(1)
Minimum
Programmable depending
Preamp
on peaking time
(2)
Rst
Shaper
Rst
Peak Hold
RstB
Programmable
(3)
Figure 11: Channel Readout Logic Timing
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