/******************************************************************* * * CAUTION: This file is automatically generated by libgen. * Version: Xilinx EDK 10.1.02 EDK_K_SP2.5 * DO NOT EDIT. * * Copyright (c) 2005 Xilinx, Inc. All rights reserved. * * Description: Driver parameters * *******************************************************************/ #define STDIN_BASEADDRESS 0x84000000 #define STDOUT_BASEADDRESS 0x84000000 /******************************************************************/ /* Definitions for peripheral XPS_BRAM_IF_CNTLR_1 */ #define XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR 0xFFFFE000 #define XPAR_XPS_BRAM_IF_CNTLR_1_HIGHADDR 0xFFFFFFFF /******************************************************************/ /* Definitions for driver UARTLITE */ #define XPAR_XUARTLITE_NUM_INSTANCES 1 /* Definitions for peripheral RS232_UART */ #define XPAR_RS232_UART_BASEADDR 0x84000000 #define XPAR_RS232_UART_HIGHADDR 0x8400FFFF #define XPAR_RS232_UART_DEVICE_ID 0 #define XPAR_RS232_UART_BAUDRATE 9600 #define XPAR_RS232_UART_USE_PARITY 0 #define XPAR_RS232_UART_ODD_PARITY 0 #define XPAR_RS232_UART_DATA_BITS 8 /******************************************************************/ /* Canonical definitions for peripheral RS232_UART */ #define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_UART_DEVICE_ID #define XPAR_UARTLITE_0_BASEADDR 0x84000000 #define XPAR_UARTLITE_0_HIGHADDR 0x8400FFFF #define XPAR_UARTLITE_0_BAUDRATE 9600 #define XPAR_UARTLITE_0_USE_PARITY 0 #define XPAR_UARTLITE_0_ODD_PARITY 0 #define XPAR_UARTLITE_0_DATA_BITS 8 #define XPAR_UARTLITE_0_SIO_CHAN -1 /******************************************************************/ /* Definitions for driver IIC */ #define XPAR_XIIC_NUM_INSTANCES 1 /* Definitions for peripheral IIC_EEPROM */ #define XPAR_IIC_EEPROM_DEVICE_ID 0 #define XPAR_IIC_EEPROM_BASEADDR 0x81600000 #define XPAR_IIC_EEPROM_HIGHADDR 0x8160FFFF #define XPAR_IIC_EEPROM_TEN_BIT_ADR 0 #define XPAR_IIC_EEPROM_GPO_WIDTH 1 /******************************************************************/ /* Canonical definitions for peripheral IIC_EEPROM */ #define XPAR_IIC_0_DEVICE_ID XPAR_IIC_EEPROM_DEVICE_ID #define XPAR_IIC_0_BASEADDR 0x81600000 #define XPAR_IIC_0_HIGHADDR 0x8160FFFF #define XPAR_IIC_0_TEN_BIT_ADR 0 #define XPAR_IIC_0_GPO_WIDTH 1 /******************************************************************/ #define XPAR_XSYSACE_MEM_WIDTH 16 /* Definitions for driver SYSACE */ #define XPAR_XSYSACE_NUM_INSTANCES 1 /* Definitions for peripheral SYSACE_COMPACTFLASH */ #define XPAR_SYSACE_COMPACTFLASH_DEVICE_ID 0 #define XPAR_SYSACE_COMPACTFLASH_BASEADDR 0x83600000 #define XPAR_SYSACE_COMPACTFLASH_HIGHADDR 0x8360FFFF #define XPAR_SYSACE_COMPACTFLASH_MEM_WIDTH 16 /******************************************************************/ /* Canonical definitions for peripheral SYSACE_COMPACTFLASH */ #define XPAR_SYSACE_0_DEVICE_ID XPAR_SYSACE_COMPACTFLASH_DEVICE_ID #define XPAR_SYSACE_0_BASEADDR 0x83600000 #define XPAR_SYSACE_0_HIGHADDR 0x8360FFFF #define XPAR_SYSACE_0_MEM_WIDTH 16 /******************************************************************/ /* Definitions for driver MPMC */ #define XPAR_XMPMC_NUM_INSTANCES 1 /* Definitions for peripheral DDR_SDRAM */ #define XPAR_DDR_SDRAM_DEVICE_ID 0 #define XPAR_DDR_SDRAM_MPMC_BASEADDR 0x00000000 #define XPAR_DDR_SDRAM_MPMC_CTRL_BASEADDR 0xFFFFFFFF #define XPAR_DDR_SDRAM_INCLUDE_ECC_SUPPORT 0 #define XPAR_DDR_SDRAM_USE_STATIC_PHY 0 #define XPAR_DDR_SDRAM_PM_ENABLE 0 #define XPAR_DDR_SDRAM_NUM_PORTS 3 /******************************************************************/ /* Definitions for peripheral DDR_SDRAM */ #define XPAR_DDR_SDRAM_MPMC_BASEADDR 0x00000000 #define XPAR_DDR_SDRAM_MPMC_HIGHADDR 0x03FFFFFF #define XPAR_DDR_SDRAM_SDMA_CTRL_BASEADDR 0x84600000 #define XPAR_DDR_SDRAM_SDMA_CTRL_HIGHADDR 0x8460FFFF /******************************************************************/ /* Canonical definitions for peripheral DDR_SDRAM */ #define XPAR_MPMC_0_DEVICE_ID XPAR_DDR_SDRAM_DEVICE_ID #define XPAR_MPMC_0_MPMC_BASEADDR 0x00000000 #define XPAR_MPMC_0_MPMC_CTRL_BASEADDR 0xFFFFFFFF #define XPAR_MPMC_0_INCLUDE_ECC_SUPPORT 0 #define XPAR_MPMC_0_USE_STATIC_PHY 0 #define XPAR_MPMC_0_PM_ENABLE 0 #define XPAR_MPMC_0_NUM_PORTS 3 /******************************************************************/ /* Definitions for driver LLTEMAC */ #define XPAR_XLLTEMAC_NUM_INSTANCES 1 /* Definitions for peripheral TRIMODE_MAC_GMII Channel 0 */ #define XPAR_TRIMODE_MAC_GMII_CHAN_0_DEVICE_ID 0 #define XPAR_TRIMODE_MAC_GMII_CHAN_0_BASEADDR 0x81c00000 #define XPAR_TRIMODE_MAC_GMII_CHAN_0_TXCSUM 0 #define XPAR_TRIMODE_MAC_GMII_CHAN_0_RXCSUM 0 #define XPAR_TRIMODE_MAC_GMII_CHAN_0_PHY_TYPE 1 /* Canonical definitions for peripheral TRIMODE_MAC_GMII Channel 0 */ #define XPAR_LLTEMAC_0_DEVICE_ID 0 #define XPAR_LLTEMAC_0_BASEADDR 0x81c00000 #define XPAR_LLTEMAC_0_TXCSUM 0 #define XPAR_LLTEMAC_0_RXCSUM 0 #define XPAR_LLTEMAC_0_PHY_TYPE 1 #define XPAR_LLTEMAC_0_INTR 3 /* LocalLink TYPE Enumerations */ #define XPAR_LL_FIFO 1 #define XPAR_LL_DMA 2 /* Canonical LocalLink parameters for TRIMODE_MAC_GMII */ #define XPAR_LLTEMAC_0_LLINK_CONNECTED_TYPE XPAR_LL_DMA #define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x84600100 #define XPAR_LLTEMAC_0_LLINK_CONNECTED_FIFO_INTR 0xFF #define XPAR_LLTEMAC_0_LLINK_CONNECTED_DMARX_INTR 2 #define XPAR_LLTEMAC_0_LLINK_CONNECTED_DMATX_INTR 1 /******************************************************************/ #define XPAR_INTC_MAX_NUM_INTR_INPUTS 7 #define XPAR_XINTC_HAS_IPR 1 #define XPAR_XINTC_USE_DCR 0 /* Definitions for driver INTC */ #define XPAR_XINTC_NUM_INSTANCES 1 /* Definitions for peripheral XPS_INTC_0 */ #define XPAR_XPS_INTC_0_DEVICE_ID 0 #define XPAR_XPS_INTC_0_BASEADDR 0x81800000 #define XPAR_XPS_INTC_0_HIGHADDR 0x8180FFFF #define XPAR_XPS_INTC_0_KIND_OF_INTR 0x00000040 /******************************************************************/ #define XPAR_INTC_SINGLE_BASEADDR 0x81800000 #define XPAR_INTC_SINGLE_HIGHADDR 0x8180FFFF #define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_0_DEVICE_ID #define XPAR_SYSTEM_FPGA_0_TRIMODE_MAC_GMII_MDINT_MASK 0X000001 #define XPAR_XPS_INTC_0_SYSTEM_FPGA_0_TRIMODE_MAC_GMII_MDINT_INTR 0 #define XPAR_DDR_SDRAM_SDMA2_TX_INTOUT_MASK 0X000002 #define XPAR_XPS_INTC_0_DDR_SDRAM_SDMA2_TX_INTOUT_INTR 1 #define XPAR_DDR_SDRAM_SDMA2_RX_INTOUT_MASK 0X000004 #define XPAR_XPS_INTC_0_DDR_SDRAM_SDMA2_RX_INTOUT_INTR 2 #define XPAR_TRIMODE_MAC_GMII_TEMACINTC0_IRPT_MASK 0X000008 #define XPAR_XPS_INTC_0_TRIMODE_MAC_GMII_TEMACINTC0_IRPT_INTR 3 #define XPAR_SYSACE_COMPACTFLASH_SYSACE_IRQ_MASK 0X000010 #define XPAR_XPS_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR 4 #define XPAR_IIC_EEPROM_IIC2INTC_IRPT_MASK 0X000020 #define XPAR_XPS_INTC_0_IIC_EEPROM_IIC2INTC_IRPT_INTR 5 #define XPAR_RS232_UART_INTERRUPT_MASK 0X000040 #define XPAR_XPS_INTC_0_RS232_UART_INTERRUPT_INTR 6 /******************************************************************/ /* Canonical definitions for peripheral XPS_INTC_0 */ #define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_0_DEVICE_ID #define XPAR_INTC_0_BASEADDR 0x81800000 #define XPAR_INTC_0_HIGHADDR 0x8180FFFF #define XPAR_INTC_0_KIND_OF_INTR 0x00000040 #define XPAR_INTC_0_MPMC_0_SDMA2_TX_INTOUT_VEC_ID XPAR_XPS_INTC_0_DDR_SDRAM_SDMA2_TX_INTOUT_INTR #define XPAR_INTC_0_MPMC_0_SDMA2_RX_INTOUT_VEC_ID XPAR_XPS_INTC_0_DDR_SDRAM_SDMA2_RX_INTOUT_INTR #define XPAR_INTC_0_LLTEMAC_0_VEC_ID XPAR_XPS_INTC_0_TRIMODE_MAC_GMII_TEMACINTC0_IRPT_INTR #define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_XPS_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR #define XPAR_INTC_0_IIC_0_VEC_ID XPAR_XPS_INTC_0_IIC_EEPROM_IIC2INTC_IRPT_INTR #define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_XPS_INTC_0_RS232_UART_INTERRUPT_INTR /******************************************************************/ /* Definitions for driver PRAYS_NUCAM_PLB46 */ #define XPAR_PRAYS_NUCAM_PLB46_NUM_INSTANCES 1 /* Definitions for peripheral PRAYS_NUCAM_PLB46_0 */ #define XPAR_PRAYS_NUCAM_PLB46_0_DEVICE_ID 0 #define XPAR_PRAYS_NUCAM_PLB46_0_MEM_BASEADDR 0x81840000 #define XPAR_PRAYS_NUCAM_PLB46_0_MEM_HIGHADDR 0x818FFFFF /******************************************************************/ #define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 /******************************************************************/ #define XPAR_CPU_ID 0 #define XPAR_PPC405_VIRTEX4_ID 0 #define XPAR_PPC405_VIRTEX4_CORE_CLOCK_FREQ_HZ 300000000 #define XPAR_PPC405_VIRTEX4_DPLB0_DWIDTH 64 #define XPAR_PPC405_VIRTEX4_DPLB0_NATIVE_DWIDTH 64 #define XPAR_PPC405_VIRTEX4_IPLB0_DWIDTH 64 #define XPAR_PPC405_VIRTEX4_IPLB0_NATIVE_DWIDTH 64 #define XPAR_PPC405_VIRTEX4_DPLB1_DWIDTH 64 #define XPAR_PPC405_VIRTEX4_DPLB1_NATIVE_DWIDTH 64 #define XPAR_PPC405_VIRTEX4_IPLB1_DWIDTH 64 #define XPAR_PPC405_VIRTEX4_IPLB1_NATIVE_DWIDTH 64 #define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_BASE 0x00000000 #define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_HIGH 0x03ffffff #define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_BASE 0x00000000 #define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_HIGH 0x03ffffff #define XPAR_PPC405_VIRTEX4_FASTEST_PLB_CLOCK DPLB0 #define XPAR_PPC405_VIRTEX4_GENERATE_PLB_TIMESPECS 1 #define XPAR_PPC405_VIRTEX4_DPLB0_P2P 0 #define XPAR_PPC405_VIRTEX4_DPLB1_P2P 1 #define XPAR_PPC405_VIRTEX4_IPLB0_P2P 0 #define XPAR_PPC405_VIRTEX4_IPLB1_P2P 1 #define XPAR_PPC405_VIRTEX4_IDCR_BASEADDR 0x00000100 #define XPAR_PPC405_VIRTEX4_IDCR_HIGHADDR 0x000001FF #define XPAR_PPC405_VIRTEX4_DISABLE_OPERAND_FORWARDING 1 #define XPAR_PPC405_VIRTEX4_MMU_ENABLE 1 #define XPAR_PPC405_VIRTEX4_DETERMINISTIC_MULT 0 #define XPAR_PPC405_VIRTEX4_PLBSYNCBYPASS 1 #define XPAR_PPC405_VIRTEX4_APU_CONTROL 0b1101111000000000 #define XPAR_PPC405_VIRTEX4_APU_UDI_1 0b101000011000100110000011 #define XPAR_PPC405_VIRTEX4_APU_UDI_2 0b101000111000100110000011 #define XPAR_PPC405_VIRTEX4_APU_UDI_3 0b101001011000100111000011 #define XPAR_PPC405_VIRTEX4_APU_UDI_4 0b101001111000100111000011 #define XPAR_PPC405_VIRTEX4_APU_UDI_5 0b101010011000110000000011 #define XPAR_PPC405_VIRTEX4_APU_UDI_6 0b101010111000110000000011 #define XPAR_PPC405_VIRTEX4_APU_UDI_7 0b101011011000110001000011 #define XPAR_PPC405_VIRTEX4_APU_UDI_8 0b101011111000110001000011 #define XPAR_PPC405_VIRTEX4_PVR_HIGH 0b0000 #define XPAR_PPC405_VIRTEX4_PVR_LOW 0b0000 #define XPAR_PPC405_VIRTEX4_HW_VER "2.01.a" /******************************************************************/ /* Linux redefines */ #define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_DDR_0_SIZE 0x4000000 #define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 #define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF #define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0