Module Status Register

The 16 bit Status Register must have the following bits to :

1. Know if the FVI is on NORMAL or TEST mode.
2. Know if each FIFO is EMPTY or not.
3. Know if each FIFO is at least HALF-FULL or not.
4. Know if the FVI has asserted INHIBIT.
5. Know if the REJECT is asserted or not.

The bit 7 and 8 of the status register are cleared after a read cycle. They are set again if the condition is true.