AGATA Digitiser Segment ADC FPGA
To download the firmware files click the correct link below for the version you require. Then use a JTAG programmer with appropriate software ( Impact from Xilinx is recommended ) to program the serial proms with the .mcs files after they are extracted from the .zip file download.
File Contents: Seg_03Mar11_#.mcs (# = 0,1,2) & Seg_03Mar11.bit
Version Number: 1.00.1.D
Version Date: 03/03/2011
Notes:
Added the MGT loopback and the SYNC diagnostics.
File Contents: Seg_03Dec10_#.mcs (# = 0,1,2)
Version Number: 1.00.1.C
Version Date: 03/12/2010
Notes:
The spare channel did not have the same ADC interface code as those in normal use. This led to data faults when crossing some bit boundaries.
File Contents: Seg_15Jan10_#.mcs (# = 0,1,2)
Version Number: 1.00.1.B
Version Date: 15/01/2010
Notes:
The Inhibit transmission is disabled by default in all six channels. It can be enabled by setting bit7 in the module control register.
File Contents: Seg_24June09_#.mcs (# = 0,1,2)
Version Number: 1.00.1.A
Version Date: 24/06/2009
For further information please e-mail Patrick.Coleman-Smith@stfc.ac.uk
