AGATA official web site

AGATA Digitiser Core ADC FPGA


To download the firmware files click the correct link below for the version you require. Then use a JTAG programmer with appropriate software ( Impact from Xilinx is recommended ) to program the serial proms with the .mcs files after they are extracted from the .zip file download.


File Contents: Core_7Oct13_dct_#.mcs (# = 0,1,2) & Core_7Oct13_DCT.bit

Version Number: 1.00.1.D

Version Date: 07/10/2013


Handles the changes for the Dual Core modification and includes the time over threshold (TOT) code. See EDOC705 for further details.


File Contents: Core_08Oct12_#.mcs (# = 0,1,2) & Core_08Oct12.bit

Version Number: 1.00.1.C

Version Date: 08/10/2012


Corrected the Digital Inspection Lines fault. Bits 12 and 13 were crossed between the two lines. See EDOC705 for further details.


File Contents: Core_03Mar11_#.mcs (# = 0,1,2) & Core_03Mar11.bit

Version Number: 1.00.1.B

Version Date: 03/03/2011


Added the loop back on the MGT. Added the SYNC diagnostics. See EDOC705 for further details.


File Contents: Core_19June_#.mcs (# = 0,1,2)

Version Number: 1.00.1.A

Version Date: 24/06/2009


Added the Trigger block to generate triggers on the isolated output. Changed the EDOC705 to include the new registers. See EDOC705 for further details.



For further information please e-mail


Simon Letts, 12 July, 2012