AGATA Digitiser FPGA Pages
The information available through these pages is intended for users of the AGATA Digitisers who wish to ensure they have the latest versions of the firmware. Each programmable logic device has a page with details of current and previous versions with information about the changes made between them.
To download the firmware files for a board open the relevant page and click the link for the version you require. Then use a JTAG programmer with appropriate software ( Impact from Xilinx is recommended ) to program the serial proms with the .mcs files after they are extracted from the .zip file download.
After July 2012 the .zip files will contain the .bit file for the FPGA. This may be used to directly program the FPGA via the MIDAS controls or a suitable JTAG programmer. Using this method doesn’t permanently change the FPGA program in the Digitiser.
Date: 30/10/2013
Notes:
New version of the Core code for the Dual Core Modification and the addition of time over threshold (TOT) on both channels.
Date: 29/10/2012
Notes:
New step-by-step programming instructions, "Program Xilinx Platform Flash via Impact". See EDOC712 for further details.
Date: 08/10/2012
Notes:
Core had a problem with Digital Inspection Lines. New version corrects it.
Date: 12/07/2012
Notes:
Updated all the files. Included the .bit file in the .zip files.
Date: 03/12/2010
Notes:
Segment has the spare channel ADC interface corrected.
Date: 15/01/2010
Notes:
Segment has the Inhibit signal transmission disabled by default.
Date: 24/06/2009
Notes:
Core FPGA has had the Trigger block added.
Date: 24/06/2009
Notes:
This file distribution system started.
For further information please e-mail Patrick.Coleman-Smith@stfc.ac.uk
